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| v3.0 TM ProASICPLUS Flash Family FPGAs Fe a t ur es an d B e ne f i ts High C apaci t y * 100% Routability and Utilization I/O * 75,000 to 1 million System Gates * 27k to 198kbits of Two-Port SRAM * 66 to 712 User I/Os Rep ro gra m m able Fl as h T ech nol ogy * * * * 0.22 4LM Flash-based CMOS Process Live at Power-Up, Single-Chip Solution No Configuration Device Required Retains Programmed Design during Power-Down/ Power-Up Cycles * Schmitt-Trigger Option on Every Input * Mixed 2.5V/3.3V Support with Individually-Selectable Voltage and Slew Rate * Bidirectional Global I/Os * Compliance with PCI Specification Revision 2.2 * Boundary-Scan Test IEEE Std. 1149.1 (JTAG) Compliant * Pin Compatible Packages across ProASICPLUS Family Uni que Cl ock Con dit io ning C ir cui tr y P erf orm a nce * 3.3V, 32-bit PCI (up to 50 MHz) * Two Integrated PLLs * External System Performance up to 150 MHz S ecur e Pr og ram m i ng * PLL with Flexible Phase, Multiply/Divide and Delay Capabilities * Internal and/or External Dynamic PLL Configuration * Two LVPECL Differential Pairs for Clock or Data Inputs S ta ndar d FP GA and AS IC De si gn F low * The Industry's Most Effective Security Key (FlashLock) Prevents Read Back of Programming Bitstream Low P ower * Low Impedance Flash Switches * Segmented Hierarchical Routing Structure * Small, Efficient, Configurable (Combinatorial or Sequential) Logic Cells Hig h P er f o r m ance R out ing H i era rc hy * Flexibility with Choice of Industry-Standard Frontend Tools * Efficient Design through Frontend Timing and Gate Optimization IS P S uppo rt * In-System Programming (ISP) via JTAG Port S RA Ms and FIFO s * Ultra-Fast Local and Long-Line Network * High Speed Very Long-Line Network * High Performance, Low Skew, Splittable Global Network Pr oA S I C PL U S P r o du ct Pr o f i l e Device APA075 Maximum System Gates 75,000 Maximum Tiles (Registers) 3,072 Embedded RAM Bits (k=1,024 bits) 27k Embedded RAM Blocks (256x9) 12 LVPECL 2 PLL 2 Global Networks 4 Maximum Clocks 24 Maximum User I/Os 158 JTAG ISP Yes PCI Yes Package (by pin count) TQFP 100, 144 PQFP 208 PBGA 144 FBGA www..com M a y 20 0 3 * ACTgen Netlist Generation Ensures Optimal Usage of Embedded Memory Blocks * 24 SRAM and FIFO Configurations with Synchronous and Asynchronous Operation up to 150 MHz (typical) APA150 150,000 6,144 36k 16 2 2 4 32 242 Yes Yes 100 208 456 144, 256 APA300 300,000 8,192 72k 32 2 2 4 32 290 Yes Yes APA450 450,000 12,288 108k 48 2 2 4 48 344 Yes Yes APA600 600,000 21,504 126k 56 2 2 4 56 454 Yes Yes APA750 750,000 32,768 144k 64 2 2 4 64 562 Yes Yes APA1000 1,000,000 56,320 198k 88 2 2 4 88 712 Yes Yes 208 456 144, 256 208 208 456 456 144, 256, 484 256, 484, 676 www..com 208 208 456 456 676, 896 896, 1152 1 *See Actel's website for the latest version of the datasheet. (c) 2003 Actel Corporation www..com Pr o A S I C P L U S F la s h F a m il y F P GA s G en er al D e sc r i p t i on The ProASICPLUS family of devices, Actel's second generation Flash FPGAs, offers enhanced performance over Actel's ProASIC family. It combines the advantages of ASICs with the benefits of programmable devices through nonvolatile Flash technology. This enables engineers to create high-density systems using existing ASIC or FPGA design flows and tools. In addition, the ProASICPLUS family offers a unique clock conditioning circuit based on two on-board phase-locked loops (PLLs). The family offers up to 1 million system gates, supported with up to 198kbits of 2-port SRAM and up to 712 user I/Os, all providing 50 MHz PCI performance. Advantages to the designer extend beyond performance. Unlike SRAM-based FPGAs, four levels of routing hierarchy simplify routing, while the use of Flash technology allows all functionality to be live at power-up. No external Boot PROM is required to support device programming. While on-board security mechanisms prevent all access to the program information, reprogramming can be performed in-system to support future design iterations and field upgrades. The device's architecture mitigates the complexity of ASIC migration at higher user volume. This makes ProASICPLUS a cost-effective solution for applications in the networking, communications, computing, and avionics markets. The ProASICPLUS family achieves its nonvolatility and reprogrammability through an advanced Flash-based 0.22m LVCMOS process with four-layers of metal. Standard CMOS design techniques are used to implement logic and control functions, including the PLLs and LVPECL inputs. This results in predictable performance fully compatible with gate arrays. The ProASICPLUS architecture provides granularity comparable to gate arrays. The device core consists of a Sea-of-Tiles. Each tile can be configured as a flip-flop, latch, or 3-input/1-output logic function by programming the appropriate Flash switches. The combination of fine granularity, flexible routing resources, and abundant Flash switches allow 100% utilization and over 95% routability for highly congested designs. Tiles and larger functions are interconnected through a 4-level routing hierarchy. Embedded 2-port SRAM blocks with built-in FIFO/RAM control logic can have user-defined depth and width. Users can also select programming for synchronous or asynchronous operation, as well as parity generations or checking. The unique clock conditioning circuitry in each device includes two clock conditioning blocks. Each block provides a PLL core, delay lines, phase shifts (0, 90, 180, 270), and clock multipliers/dividers, as well as the circuitry needed to provide bidirectional access to the PLL. The PLL block contains four programmable frequency dividers, which allow the incoming clock signal to be divided by a wide range of factors from 1 to 64. The clock conditioning circuit also delays or advances the incoming reference clock up to 8 ns (in increments of 0.25 ns). The PLL can be configured internally or externally during operation without redesigning or reprogramming the part. In addition to the PLL, there are two LVPECL differential input pairs to accommodate high speed clock and data inputs. To support customer needs for more comprehensive, lower cost board-level testing, Actel's ProASICPLUS devices are fully compatible with IEEE Standard 1149.1 for test access port and boundary-scan test architecture. For more information concerning the Flash FPGA implementation, please refer to the "Boundary Scan (JTAG)" section on page 13. ProASICPLUS devices are available in a variety of high-performance plastic packages. Those packages and the performance features discussed above are described in more detail in the following sections. 2 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s O r d e r i n g I nf o r m a t i o n _ APA1000 F FG 1152 I Application (Ambient Temperature Range) Blank = Commercial (0 to +70 C) I = Industrial (-40 to +85 C) PP = Pre-production ES = Engineering Silicon (Room Temperature Only) Package Lead Count Package Type TQ = Thin Quad Flat Pack (1.4mm pitch) PQ = Plastic Quad Flat Pack (0.5mm pitch) FG = Fine Pitch Ball Grid Array (1.0mm pitch) BG = Plastic Ball Grid Array (1.27mm pitch) Speed Grade Blank = Standard Speed F = 20% Slower than Standard Part Number APA075 APA150 APA300 APA450 APA600 APA750 APA1000 = = = = = = = 75,000 Equivalent System Gates 150,000 Equivalent System Gates 300,000 Equivalent System Gates 450,000 Equivalent System Gates 600,000 Equivalent System Gates 750,000 Equivalent System Gates 1,000,000 Equivalent System Gates Pl a s t i c D e vi c e Re so u r ce s User I/Os* Device APA075 APA150 APA300 APA450 APA600 APA750 APA1000 TQFP 100-Pin 66 66 TQFP 144-Pin 107 PQFP 208-Pin 158 158 158 158 158 158 158 242 290 344 356 356 356 PBGA 456-Pin FBGA 144-Pin 100 100 100 100 186 186 186 186 344 370 454 454 562 642 712 FBGA 256-Pin FBGA 484-Pin FBGA 676-Pin FBGA 896-Pin FBGA 1152-Pin Package Definitions TQFP = Thin Quad Flat Pack, PQFP = Plastic Quad Flat Pack, PBGA = Plastic Ball Grid Array, FBGA = Fine Pitch Ball Grid Array *Each pair of PECL I/Os were counted as one user I/O. v3.0 3 Pr o A S I C P L U S F la s h F a m il y F P GA s Pr od uc t A va i l a bi l i t y Speed Grade Std. APA075 Device 100-Pin Thin Quad Flat Pack (TQFP) 144-Pin Thin Quad Flat Pack (TQFP) 208-Pin Plastic Quad Flat Pack (PQFP) 144-Pin Fine Pitch Ball Grid Array (FBGA) APA150 Device 100-Pin Thin Quad Flat Pack (TQFP) 208-Pin Plastic Quad Flat Pack (PQFP) 456-Pin Plastic Ball Grid Array (PBGA) 144-Pin Fine Pitch Ball Grid Array (FBGA) 256-Pin Fine Pitch Ball Grid Array (FBGA) APA300 Device 208-Pin Plastic Quad Flat Pack (PQFP) 456-Pin Plastic Ball Grid Array (PBGA) 144-Pin Fine Pitch Ball Grid Array (FBGA) 256-Pin Fine Pitch Ball Grid Array (FBGA) APA450 Device 208-Pin Plastic Quad Flat Pack (PQFP) 456-Pin Plastic Ball Grid Array (PBGA) 144-Pin Fine Pitch Ball Grid Array (FBGA) 256-Pin Fine Pitch Ball Grid Array (FBGA) 484-Pin Fine Pitch Ball Grid Array (FBGA) APA600 Device 208-Pin Plastic Quad Flat Pack (PQFP) 456-Pin Plastic Ball Grid Array (PBGA) 256-Pin Fine Pitch Ball Grid Array (FBGA) 484-Pin Fine Pitch Ball Grid Array (FBGA) 676-Pin Fine Pitch Ball Grid Array (FBGA) APA750 Device 208-Pin Plastic Quad Flat Pack (PQFP) 456-Pin Plastic Ball Grid Array (PBGA) 676-Pin Fine Pitch Ball Grid Array (FBGA) 896-Pin Plastic Ball Grid Array (FBGA) APA1000 Device 208-Pin Plastic Quad Flat Pack (PQFP) 456-Pin Plastic Ball Grid Array (PBGA) 896-Pin Fine Pitch Ball Grid Array (FBGA) Application C I -F* PP PP PP PP 1152-Pin Fine Pitch Ball Grid Array (FBGA) Note: *-F parts are only available as commercial temperature devices. Applications: C = Commercial I = Industrial Availability: = Available PP = Product Planned 4 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s Pr oA S I C PL U S A r c hi t e c t u r e The proprietary ProASICPLUS architecture granularity comparable to gate arrays. provides the "Embedded Memory Configurations" section on page 21 for more information. Fla sh S wit ch The ProASICPLUS device core consists of a Sea-of-TilesTM (Figure 1). Each tile can be configured as a 3-input logic function (e.g., NAND gate, D-Flip-Flop, etc.) by programming the appropriate Flash switch interconnections (Figure 2 on page 6 and Figure 3 on page 6). Tiles and larger functions are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming. Flash switches are programmed to connect signal lines to the appropriate logic cell inputs and outputs. Dedicated high-performance lines are connected as needed for fast, low-skew global signal distribution throughout the core. Maximum core utilization is possible for virtually any design. ProASICPLUS devices also contain embedded two-port SRAM blocks with built-in FIFO/RAM control logic. Programming options include synchronous or asynchronous operation, two-port RAM configurations, user defined depth and width, and parity generation or checking. Please see Unlike SRAM FPGAs, ProASICPLUS uses a live on power-up ISP Flash switch as its programming element. In the ProASICPLUS Flash switch, two transistors share the floating gate, which stores the programming information. One is the sensing transistor, which is only used for writing and verification of the floating gate voltage. The other is the switching transistor. It can be used in the architecture to connect/separate routing nets or to configure logic. It is also used to erase the floating gate (Figure 2 on page 6). Logi c Ti le The logic tile cell (Figure 3 on page 6) has three inputs (any or all of which can be inverted) and one output (which can connect to both ultra-fast local and efficient long-line routing resources). Any three-input, one-output logic function (except a three-input XOR) can be configured as one tile. The tile can be configured as a latch with clear or set or as a flip-flop with clear or set. Thus, the tiles can flexibly map logic and sequential gates of a design. RAM Block 256x9 Two-Port SRAM or FIFO Block I/Os Logic Tile RAM Block 256x9 Two Port SRAM or FIFO Block Figure 1 * The ProASICPLUS Device Architecture v3.0 5 Pr o A S I C P L U S F la s h F a m il y F P GA s Floating Gate Switch In Sensing Switching Word Switch Out Figure 2 * Flash Switch Local Routing In 1 Efficient Long-Line Routing In 2 (CLK) In 3 (Reset) Figure 3 * Core Logic Tile Rou ti ng Res our ces The routing structure of ProASICPLUS devices is designed to provide high performance through a flexible four-level hierarchy of routing resources: ultra-fast local resources, efficient long-line resources, high speed very long-line resources, and high performance global networks. The ultra-fast local resources are dedicated lines that allow the output of each tile to connect directly to every input of the eight surrounding tiles (Figure 4 on page 7). The efficient long-line resources provide routing for longer distances and higher fanout connections. These resources vary in length (spanning 1, 2, or 4 tiles), run both vertically and horizontally, and cover the entire ProASICPLUS device (Figure 5 on page 7). Each tile can drive signals onto the efficient long-line resources, which can in turn, access every input of every tile. Active buffers are inserted automatically by routing software to limit the loading effects due to distance and fanout. The high-speed very long-line resources, which span the entire device with minimal delay, are used to route very long or very high fanout nets. (Figure 6 on page 8). The high-performance global networks are low skew, high fanout nets that are accessible from external pins or from internal logic (Figure 7 on page 9). These nets are typically used to distribute clocks, resets, and other high fanout nets requiring a minimum skew. The global networks are implemented as clock trees, and signals can be introduced at any junction. These can be employed hierarchically with signals accessing every input on all tiles. 6 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s L L L L Inputs L Output L Ultra-Fast Local Lines (connects a tile to the adjacent tile, I/O buffer, or memory block) L L L Figure 4 * Ultra-Fast Local Resources Spans 4 Tiles Spans 2 Tiles Spans 1 Tile Logic Tile L L L L L L L L L L L L L L L L L L Spans 1 Tile Spans 2 Tiles Spans 4 Tiles L L L L L L Logic Cell L L L L L L Figure 5 * Efficient Long-Line Resources v3.0 7 Pr o A S I C P L U S F la s h F a m il y F P GA s High Speed Very Long-Line Resouces PAD RING SRAM PAD RING I/O RING I/O RING SRAM PAD RING Figure 6 * High Speed Very Long-Line Resources 8 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s The ProASIC family offers powerful and flexible control of circuit timing through the use of analog circuitry. Each chip has two clock conditioning blocks containing a phase-locked loop (PLL) core, delay lines, phase shifter (0, 90, 180, 270), clock multiplier/dividers and all the circuitry needed for the selection and interconnection of inputs to the global network (thus providing bidirectional access to the PLL). This permits the PLL block to drive inputs and/or outputs via the two global lines on each side of the chip (four total lines). This circuitry is discussed in more detail in the "ProASICPLUS Clock Management System" section on page 15. Cl ock T ree s Cl ock Res our ce s PLUS based on a network of spines and ribs that reach all the tiles in their regions (Figure 7). This flexible clock tree architecture allows users to map up to 88 different internal/external clocks in an APA1000 device. Details on the clock spines and various numbers of the family are given in Table 1 on page 10. The flexible use of the ProASICPLUS clock spine allows the designer to cope with several design requirements. Users implementing clock resource intensive applications can easily route external or gated internal clocks using global routing spines. Users can also drastically reduce delay penalties and save buffering resources by mapping critical high-fanout nets to spines. For design hints on using these features, refer to Actel's Efficient Use of ProASIC Clock Trees application note. One of the main architectural benefits of ProASICPLUS is the set of power and delay friendly global networks. ProASICPLUS offers four global trees. Each of these trees is High Performace Global Network PAD RING PAD RING I/O RING Top Spine Global Networks Global Pads Global Pads Global Spine Global Ribs Bottom Spine I/O RING Scope of Spine (Shaded area plus local RAMs and I/Os) PAD RING Note: This figure shows routing for only one global path. Figure 7 * High Performance Global Network v3.0 9 Pr o A S I C P L U S F la s h F a m il y F P GA s Table 1 * Clock Spines APA075 Global Clock Networks (Trees) Clock Spines/Tree Total Spines Top or Bottom Spine Height (Tiles) Tiles in Each Top or Bottom Spine Total Tiles Ar r ay Co ord ina tes APA150 4 8 32 24 768 6,144 APA300 4 8 32 32 1,024 8,192 APA450 4 12 48 32 1,024 12,288 APA600 4 14 56 48 1,536 21,504 APA750 4 16 64 64 2,048 32,768 APA1000 4 22 88 80 2,560 56,320 4 6 24 16 512 3,072 During many place-and-route operations in Actel's Designer software tool, it is possible to set constraints that require array coordinates. Table 2 is provided as a reference. The array coordinates are measured from the lower left (0,0). They can be used in region constraints for specific groups, designated by a wildcard, and containing core cells, I/Os, and memories. I/O and cell coordinates are used for placement constraints. Two coordinate systems are needed because there is not a Table 2 * Array Coordinates Logic Tile Min. Device APA075 APA150 APA300 APA450 APA600 APA750 APA1000 x 1 1 1 1 1 1 1 y 1 1 5 5 5 5 5 x 96 128 128 192 224 256 352 Max. y 32 48 68 68 100 132 164 one-to-one correspondence between I/O cells and core cells. In addition, the I/O coordinate system changes depending on the die/package combination. Core cell coordinates start at the lower left corner (1,1) or (1,5) if memories are present at the bottom. Memory coordinates use the same system and are indicated in Table 2. The memory coordinates for an APA1000 are illustrated in Figure 8. For more information on how to use constraints, see the Designer User's Guide for ProASICPLUS software tools. Memory Rows Bottom y - - (1,3) or (1,5) (1,3) or (1,5) (1,3) or (1,5) (1,3) or (1,5) (1,3) or (1,5) Top y (33,33) or (33, 35) (49,49) or (49, 51) (69,69) or (69, 71) (69,69) or (69, 71) (101,101) or (101, 103) (133,133) or (133, 135) (165,165) or (165, 167) Min. 0,0 0,0 0,0 0,0 0,0 0,0 0,0 All Max. 97, 37 129, 53 129, 73 193, 73 225, 105 257, 137 353, 169 Memory Blocks (1,169) (1,167) (1,165) (1,164) Core (353,169) (352,167) (352,165) (352,165) (1,5) (1,3) (1,1) (0,0) Memory Blocks (352,5) (352,3) (352,1) (353,0) Figure 8 * Core Cell Coordinates for the APA1000 10 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s Inpu t/ Out put Blo cks To meet complex system demands, the ProASICPLUS family offers devices with a large number of user I/O pins, up to 712 on the APA1000. If the I/O pad power supply (VDDP) is 3.3V, each I/O can be selectively configured at the 2.5V and 3.3V threshold levels. Table 3 shows the available supply voltage configurations (the PLL block uses an independent 2.5V supply on the AVDD and AGND pins). All I/Os include ESD protection circuits. Each I/O has been tested to 2000V to the human body model (per JESD22 (HMB)). Table 3 * ProASICPLUS I/O Power Supply Voltages VDDP 2.5V Input Compatibility Output Drive Note: VDD is always 2.5V. 2.5V 2.5V 3.3V 3.3V, 2.5V 3.3V, 2.5V Six or seven standard I/O pads are grouped with a GND pad and either a VDD (core power) or VDDP (I/O power) pad. Two reference bias signals circle the chip. One protects the cascaded output drivers while the other creates a virtual VDD supply for the I/O ring. I/O pads are fully configurable to provide the maximum flexibility and speed. Each pad can be configured as an input, an output, a tristate driver, or a bidirectional buffer (Figure 9 and Table 4). 3.3V/2.5V Signal Control Pull-up Control Y EN A Pad 3.3V/2.5V Signal Control Drive Strength and Slew-Rate Control Figure 9 * I/O Block Schematic Representation Table 4 * I/O Features Function I/O pads configured as inputs Description * Individually selectable 2.5V or 3.3V threshold levels * Optional pull-up resistor * Optionally configurable as Schmitt trigger input. The Schmitt trigger input option can be configured as an input only, not a bidirectional buffer. This input type may be slower than a standard input under certain conditions and has a typical hysteresis of 0.35V. I/O macros with an "S" in the standard I/O library have added Schmitt capabilities I/O pads configured as outputs * 3.3V PCI Compliant * Individually selectable 2.5V or 3.3V compliant output signals - 2.5V - JEDEC JESD 8-5 - 3.3V - JEDEC JESD 8-A (LVTTL and LVCMOS) * 3.3V PCI compliant * Ability to drive LVTTL and LVCMOS levels * Selectable drive strengths * Selectable slew rates I/O pads configured as bidirectional buffers * Tristate * Individually selectable 2.5V or 3.3V compliant output signals - 2.5V - JEDEC JESD 8-5 - 3.3V - JEDEC JESD 8-A (LVTTL and LVCMOS) * 3.3V PCI compliant * Optional pull-up resistor * Selectable drive strengths * Selectable slew rates * Tristate v3.0 11 Pr o A S I C P L U S F la s h F a m il y F P GA s While ProASIC devices are live at power-up, the order of VDD and VDDP power-up is important during system start-up. VDD should be powered up before (or coincident with) VDDP on ProASICPLUS devices. Failure to follow these guidelines may result in undesirable pin behavior during system start-up. For more information, refer Actel's ProASICPLUS Family Devices Power-Up Behavior application note. LVP E C L Inp ut P ads P ower -u p S eq uenci ng PLUS PPECL (I/P) (PECLN) and NPECL (PECLREF). The LVPECL input pad cell differs from the standard I/O cell in that it is operated from VDD only. Since it is exclusively an input, it requires no output signal, output enable signal, or output configuration bits. As a special high-speed differential input, it also does not require pull ups. Recommended termination for LVPECL inputs is shown in Figure 10. The LVPECL pad cell compares voltages, as illustrated in Figure 11, on the PPECL (I/P) pad and the NPECL pad and sends the results to the global MUX (Figure 14 on page 16). This high speed, low skew output essentially controls the clock conditioning circuit. LVPECLs are designed to meet LVPECL JEDEC receiver standard levels (Table 5). In addition to standard I/O pads and power pads, ProASICPLUS devices have a single LVPECL input pad on both the east and west sides of the device, along with AVDD and AGND pins to power the PLL block. The LVPECL pad cell consists of an input buffer (containing a low voltage differential amplifier) and a signal and its complement, Z 0 = 50 PPECL + From LVPECL Driver Z 0 = 50 NPECL R = 100 _ Data Figure 10 * Recommended Termination for LVPECL Inputs Voltage 2.72 2.125 1.49 0.86 Figure 11 * LVPECL High and Low Threshold Values Table 5 * LVPECL Receiver Specifications Symbol VIH VIL VID Parameter Input High Voltage Input Low Voltage Differential Input Voltage Min. 1.49 0.86 0.3 Max 2.72 2.125 VDD Units V V V 12 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s Boundary Scan (JTAG) ProASICPLUS devices are compatible with IEEE Standard 1149.1, which defines a set of hardware architecture and mechanisms for cost-effective board-level testing. The basic ProASICPLUS boundary-scan logic circuit is composed of the TAP (test access port), TAP controller, test data registers, and instruction register (Figure 12). This circuit supports all mandatory IEEE 1149.1 instructions (EXTEST, SAMPLE/PRELOAD and BYPASS) and the optional IDCODE instruction (Table 6). Each test section is accessed through the TAP, which has five associated pins: TCK (test clock input), TDI and TDO (test data input and output), TMS (test mode selector) and TRST (test reset input). TMS, TDI and TRST are equipped with pull-up resistors to ensure proper operation when no input data is supplied to them. These pins are dedicated for boundary-scan test usage. Actel recommends that a nominal 20k pull-up resistor is added to TDO and TCK pins. The TAP controller is a four-bit state machine (16 states) that operates as shown in Figure 13 on page 14. The `1's and `0's represent the values that must be present at TMS at a rising edge of TCK for the given state transition to occur. IR and DR indicate that the instruction register or the data register is operating in that state. ProASICPLUS devices have to be programmed at least once for complete boundary-scan functionality to be available. If boundary-scan functionality is required prior to partial programming, refer to online technical support on the Actel website and search for ProASICPLUS BSDL. I/O I/O I/O I/O I/O Test Data Registers TDI TCK TMS TAP Controller Instruction Register Device Logic TRST TDO I/O I/O I/O I/O I/O Figure 12 * ProASICPLUS JTAG Boundary Scan Test Logic Circuit Table 6 * Boundary-Scan Opcodes Hex Opcode EXTEST SAMPLE/PRELOAD IDCODE CLAMP BYPASS 00 01 0F 05 FF v3.0 I/O I/O I/O I/O Bypass Register 13 Pr o A S I C P L U S F la s h F a m il y F P GA s The TAP controller receives two control inputs (TMS and TCK) and generates control and clock signals for the rest of the test logic architecture. On power-up, the TAP controller enters the Test-Logic-Reset state. To guarantee a reset of the controller from any of the possible states, TMS must remain high for five TCK cycles. The TRST pin may also be used to asynchronously place the TAP controller in the Test-Logic-Reset state. ProASICPLUS devices support three types of test data registers: bypass, device identification, and boundary scan. The bypass register is selected when no other register needs to be accessed in a device. This speeds up test data transfer to other devices in a test data path. The 32-bit device identification register is a shift register with four fields (lowest significant byte (LSB), ID number, part number and version). The boundary-scan register observes and controls the state of each I/O pin. Each I/O cell has three boundary-scan register cells, each with a serial-in, serial-out, parallel-in, and parallel-out pin. The serial pins are used to serially connect all the boundary-scan register cells in a device into a boundary-scan register chain, which starts at the TDI pin and ends at the TDO pin. The parallel ports are connected to the internal core logic tile and the input, output, and control ports of an I/O buffer to capture and load data into the register to control or observe the logic state of each I/O. 1 Test-Logic Reset 0 Run-Test/ Idle 1 Select-DRScan 0 1 Capture-DR 0 0 1 Select-IRScan 0 1 0 1 Capture-IR 0 Shift-IR 1 1 0 Exit-IR 0 Pause-IR 1 0 Exit2-IR 1 Update-IR 1 0 1 0 Shift-DR 1 Exit-DR 0 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 0 1 Figure 13 * TAP Controller State Diagram 14 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s Ti m i ng C on t r o l an d Ch a r ac t e r i s t i cs P roA S I C P L U S Cl ock Man agem en t S ys te m Global B Introduction * Output from Global MUX B * Delayed or advanced version of fOUT * Divided version of either of the above * Further delayed version of either of the above (0.25 ns, 0.50 ns, or 4.00 ns delay)1 Func ti onal D es cr ipt io n ProASICPLUS devices provide designers with very flexible clock conditioning capabilities. Each member of the ProASICPLUS family contains two phase-locked loop (PLL) blocks which perform the following functions: * Clock Phase Adjustment via Programmable Delay (250 ps steps from -8 ns to +8 ns) * Clock Skew Minimization * Clock Frequency Synthesis Each PLL has the following key features: * Input Frequency Range (fIN) = 1.5 to 180 MHz * Feedback Frequency Range (fVCO) = 1.5 to 180 MHz * Output Frequency Range (fOUT) = 6 to 180 MHz * Output Phase Shift = 0 , 90 , 180 , and 270 * Output Duty Cycle = 50% * Low Output Jitter (max at 25 C) - fVCO <10 MHz. Jitter 1% or better - 10 MHz < fVCO < 60 MHz. Jitter 2% or better - fVCO > 60 MHz. Jitter 1% or better * Maximum Acquisition Time = 80s * Low Power Consumption - 6.9 mW (max - analog supply) + 7.0W/MHz (max - digital supply) P hys ic al Im ple m ent at ion Each PLL block contains four programmable dividers as shown in Figure 14 on page 16. These allow frequency scaling of the input clock signal as follows: * The n divider divides the input clock by integer factors from 1 to 32. * The m divider in the feedback path allows multiplication of the input clock by integer factors ranging from 1 to 64. * The two dividers together can implement any combination of multiplication and division resulting in a clock frequency between 24 and 180 MHz exiting the PLL core. This clock has a fixed 50% duty cycle. * The output frequency of the PLL core is given by the following formula (fREF is the reference clock frequency): fOUT = fREF * m/n * The third and fourth dividers (u and v) permit the signals applied to the global network to each be further divided by integer factors ranging from 1 to 4. The implementations: fGLB = m/(n*u) fGLA = m/(n*v) enable the user to define a wide range of frequency multipliers and divisors. The clock conditioning circuit can advance or delay the clock up to 8 ns (in increments of 0.25 ns) relative to the positive edge of the incoming reference clock. The system also allows for the selection of output frequency clock phases of 0, 90, 180, and 270. Prior to the application of signals to the rib drivers, they pass through programmable delay units, one per global network. These units permit the delaying of global signals relative to other signals to assist in the control of input set-up times. Not all possible combinations of input and output modes can be used. The degrees of freedom available in the bidirectional global pad system and in the clock conditioning circuit have been restricted. This avoids unnecessary and unwieldy design kit and software work. Each side of the chip contains a clock conditioning circuit based upon a 180 MHz PLL block (Figure 14 on page 16). Two global multiplexed lines extend along each side of the chip to provide bidirectional access to the PLL on that side (neither MUX can be connected to the opposite side's PLL). Each global line has optional LVPECL input pads (described below). The global lines may be driven by either the LVPECL global input pad or the outputs from the PLL block or both. Each global line can be driven by a different output from the PLL. Unused global pins can be configured as regular I/Os or left unconnected. They default to an input with pull-up. The two signals available to drive the global networks are as follows (Figure 15 on page 17): Global A (secondary clock) * Output from Global MUX A * Conditioned version of PLL output (fOUT) - delayed or advanced * Divided version of either of the above * Further delayed version of either of the above (0.25 ns, 0.50 ns, or 4.00 ns delay)1 1. This mode is available through the delay feature of the Global MUX driver. v3.0 15 Pr o A S I C P L U S F la s h F a m il y F P GA s Lock Signal A Lock signal (Active High) is provided (using the ACTgen PLL development tool) to indicate that the PLL has locked to the incoming clock signal. Users can employ the Lock signal as a soft reset of the logic driven by GLB and/or GLA. P LL C onfi gur at io n Op ti ons The PLL can be configured during design (via Flash-configuration bits set in the programming bitstream) or dynamically during device operation, thus eliminating the need for complete reprogramming. The dynamic configuration bits are loaded into a serial-in/parallel-out shift register provided in the clock conditioning circuit of AVDD each PLL and then latched into the PLL block. The JTAG ports can be used along with a built-in user JTAG interface hardware to load the configuration shift register externally. Another option is internal dynamic configuration via userdesigned hardware. Refer to Actel's ProASICPLUS PLL Dynamic Reconfiguration Using JTAG application note for more information. For information on the clock conditioning circuit, refer to the, Actel's Using ProASICPLUS Clock Conditioning Circuits application note. AGND VDD GND Global MUX B OUT Input Pins to the PLL See Figure 13 + on page 17 External Feedback Signal Clock Conditioning Circuitry (Top level view) GLA GLB 27 4 8 Flash Configuration Bits Dynamic Configuration Bits Global MUX A OUT Clock Conditioning Circuitry Detailed Block Diagram Global MUX B OUT /n PLL Core /m 270 180 90 0 /u DLYB D 2 GLB FBDLY D External Feedback 1 DLYAFB D 2 /v Global MUX A OUT DLYA2 D GLA Notes: 1. FBDLY is a programmable delay line from 0 to 4 ns in 250 ps increments. 2. DLYA, DLYB, DLYAFB is a programmable delay line with values 0, 250 ps, 500 ps, and 4 ns. Figure 14 * PLL Block - Top-Level View and Detailed PLL Block Diagram 16 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s Package Pins GL NPECL Physical I/O Buffers Std. Pad Cell PECL Pad Cell Global MUX Configuration Tile Global MUX B OUT PPECL External Feedback Global MUX A OUT Configuration Tile GLMX GL Std. Pad Cell Std. Pad Cell CORE Legend Physical Pin DATA Signals to the Core DATA Signals to the PLL Block DATA Signals to the Global MUX Control Signals to the Global MUX Note: When a signal from an I/O tile is connected to the core, it cannot be connected to the Global MUX at the same time. Figure 15 * Input Connectors to ProASICPLUS Clock Conditioning Circuitry Sa m p l e I m pl e m e nt a t i o ns Fr eque ncy S yn th esi s C l oc k S k ew M i n i m i z ati o n Figure 16 on page 18 illustrates an example where the PLL is used to multiply a 33 MHz external clock up to 133 MHz. Figure 17 on page 18 uses two dividers to synthesize a 50 MHz output clock from a 40 MHz input reference clock. The input frequency of 40 MHz is multiplied by 5 and divided by 4, giving an output clock (GLB) frequency of 50 MHz. When dividers are used, a given ratio can be generated in multiple ways, allowing the user to stay within the operating frequency ranges of the PLL. For example, in this case the input divider could have been 2 and the output divider also 2, giving us a division of the input frequency by 4 to go with the feedback loop division (effective multiplication) by 5. A dj u st a b l e C l o ck D el a y Figure 20 on page 20 indicates how feedback from the clock network can be used to create minimal skew between the distributed clock network and the "input" clock. The input clock is fed to the reference clock input of the PLL. The output clock (GLA) feeds a clock network. The feedback input to the PLL uses a clock input delayed by a routing network. The PLL then adjusts the phase of the input clock to match the delayed clock, thus providing nearly zero effective skew between the two clocks. Refer to Actel's Using ProASICPLUS Clock Conditioning Circuits application note for more information. fall into three categories: family dependent, device dependent, and design dependent. The input and output buffer characteristics are common to all ProASICPLUS family members. Internal routing delays are device dependent. Design dependency means that actual delays are not determined until after placement and routing of the user's design are complete. Delay values may then be determined by using the Timer utility or performing simulation with post-layout delays. Logi c Ti le T im i ng C har act er i st ics Timing characteristics for ProASICPLUS devices Figure 18 on page 19 illustrates the delay of the input clock by employing one of the adjustable delay lines. This is easily done in ProASICPLUS by bypassing the PLL core entirely and using the output delay line. Notice also that the output clock can be effectively advanced relative to the input clock by using the delay line in the feedback path. This is shown in Figure 19 on page 19. v3.0 17 Pr o A S I C P L U S F la s h F a m il y F P GA s Cr it ic al Net s and T ypi cal Ne ts Propagation delays are expressed only for typical nets, which are used for initial design performance evaluation. Critical net delays can then be applied to the most timing critical paths. Critical nets are determined by net property assignment prior to placement and routing. Refer to the Actel Designer User's Guide for details on using constraints. Since ProASIC devices are manufactured with a CMOS process, device performance will vary with temperature, voltage, and process. Minimum timing parameters reflect maximum operating voltage, minimum operating temperature, and optimal process variations. Maximum timing parameters reflect minimum operating voltage, maximum operating temperature, and worst-case process variations (within process specifications). T im i ng Der at in g PLUS Global MUX B OUT 33 MHz /1 /n PLL Core /m /4 270 180 90 0 /u /1 D 133 MHz GLB D D External Feedback /v Global MUX A OUT D GLA Figure 16 * Using the PLL 33 MHz In, 133 MHz Out Global MUX B OUT 40 MHz /4 /n PLL Core /m /5 270 180 90 0 /u /1 GLB D 50 MHz D D External Feedback /v Global MUX A OUT D GLA Figure 17 * Using the PLL 40 MHz In, 50 MHz Out 18 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s Global MUX B OUT 133 MHz /1 /n PLL Core /m /1 270 180 90 0 /u /1 D 133 MHz GLB D D External Feedback /v Global MUX A OUT D GLA Figure 18 * Using the PLL to Delay the Input Clock Global MUX B OUT 133 MHz /1 /n PLL Core /m /1 270 180 90 0 /u /1 GLB D 133 MHz D D External Feedback /v Global MUX A OUT D GLA Figure 19 * Using the PLL to "Advance" the Input Clock v3.0 19 Pr o A S I C P L U S F la s h F a m il y F P GA s Global MUX B OUT 133 MHz /1 /n PLL Core /m /1 270 180 90 0 /u /1 D GLB D D External Feedback /v Global MUX A OUT 133 MHz D GLA Q SET D Q CLR Figure 20 * Using the PLL for Clock De-skewing 20 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s PL L El e c t r i c al S pe c i f i c at i o n s Parameter Frequency Ranges Reference Frequency fIN (min.) Reference Frequency fIN (max.) OSC Frequency fVCO (min.) OSC Frequency fVCO (max.) Clock Conditioning Circuitry fOUT (min.) Clock Conditioning Circuitry fOUT (max.) Long Term Jitter Peak-to-Peak Max. Temperature 25C (or higher) 0C -40C Acquisition Time from Cold Start Acquisition Time (max.) Acquisition Time (max.) Power Consumption Analog Supply Power (max*) Digital Supply Current (max) Duty Cycle Note: TM Value 1.5 MHz 180 MHz 24 MHz 180 MHz 6 MHz 180 MHz Notes Clock conditioning circuitry (min.) lowest output frequency Clock conditioning circuitry (max.) highest output frequency Lowest output frequency voltage controlled oscillator Highest output frequency voltage controlled oscillator Lowest input frequency clock conditioning circuitry Highest input frequency clock conditioning circuitry Frequency MHz fVCO<10 10 *High clock frequency ProASIC devices have FlashLock protections bits that, once programmed, block the entire programmed contents from being read externally. If locked, the user can only reprogram the device employing the user-defined security key. This protects the device from being read back and duplicated. Since programmed data is stored in nonvolatile memory cells (which are actually very small capacitors), rather than in the wiring, physical deconstruction cannot be used to compromise data. This approach is further hampered by the placement of the memory cells beneath the four metal layers (whose removal cannot be accomplished without disturbing the charge in the capacitor). This is the highest security provided in the industry. For more information, refer to Actel's Design Security in Nonvolatile Flash and Antifuse FPGAs white paper. E m bedde d M em or y Flo orp lan U se r S e c u r it y PLUS be programmed as an independent memory or combined (using dedicated memory routing resources) to form larger, more complex memories. A single memory configuration cannot include blocks from both the top and bottom memory locations. provides great configuration flexibility (Table 7 on page 22). Unlike many other programmable vendors each ProASICPLUS block is designed and optimized as a two-port memory (1 read, 1 write). This provides 198kbits of total memory for two-port and single port usage in the APA1000 device. Each memory can be configured as FIFO or SRAM, with independent selection of synchronous or asynchronous read and write ports (Table 8 on page 22). Additional characteristics include programmable flags as well as parity checking and generation. Figure 21 on page 23 and Figure 22 on page 24 show the block diagrams of the basic SRAM and FIFO blocks. Table 9 on page 23 and Table 10 on page 24 describe memory block SRAM and FIFO interface signals, respectively. A single memory is designed to operate E m bedde d M em or y Con f igu rat i ons The embedded memory in the ProASICPLUS family The embedded memory is located across the top and bottom of the device in 256x9 blocks (Figure 1 on page 5). Depending upon the device, up to 88 blocks are available to support a variety of memory configurations. Each block can v3.0 21 Pr o A S I C P L U S F la s h F a m il y F P GA s at up to 150 MHz (standard speed grade typical conditions). Each block contains a 256 word, 9-bit wide (1 read port, 1 write port) memory. The memory blocks may be combined in parallel to form wider memories or stacked to form deeper memories (Figure 23 on page 25). This provides optimal bit widths of 9 (1 block), 18, 36, and 72, and optimal depths of 256, 512, 768, and 1,024. Refer to Actel's A Guide to ACTgen Macros for more information. Table 7 * ProASICPLUS Memory Configurations by Device Figure 24 on page 25 gives an example of optimal memory usage. Ten blocks with 23,040 bits have been used to generate three memories of various widths and depths. Figure 25 on page 25 shows how memory can be used in parallel to create extra read ports. In this example, using only 10 of the 88 available blocks of the APA1000 yields an effective 6,912 bits of multiple port memories. The Actel ACTgen software facilitates building wider and deeper memories for optimal memory usage. Maximum Width Device APA075 APA150 APA300 APA450 APA600 APA750 APA1000 Bottom 0 0 16 24 28 32 44 Top 12 16 16 24 28 32 44 D 256 256 256 256 256 256 256 W 108 144 144 216 252 288 396 Maximum Depth D 1,536 2,048 2,048 3,072 3,584 4,096 5,632 W 9 9 9 9 9 9 9 Table 8 * Basic Memory Configurations Type RAM RAM RAM RAM RAM RAM RAM RAM RAM RAM RAM RAM FIFO FIFO FIFO FIFO FIFO FIFO FIFO FIFO FIFO FIFO FIFO FIFO Write Access Asynchronous Asynchronous Asynchronous Asynchronous Asynchronous Asynchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Asynchronous Asynchronous Asynchronous Asynchronous Asynchronous Asynchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Read Access Asynchronous Asynchronous Synchronous Transparent Synchronous Transparent Synchronous Pipelined Synchronous Pipelined Asynchronous Asynchronous Synchronous Transparent Synchronous Transparent Synchronous Pipelined Synchronous Pipelined Asynchronous Asynchronous Synchronous Transparent Synchronous Transparent Synchronous Pipelined Synchronous Pipelined Asynchronous Asynchronous Synchronous Transparent Synchronous Transparent Synchronous Pipelined Synchronous Pipelined Parity Checked Generated Checked Generated Checked Generated Checked Generated Checked Generated Checked Generated Checked Generated Checked Generated Checked Generated Checked Generated Checked Generated Checked Generated Library Cell Name RAM256x9AA RAM256x9AAP RAM256x9AST RAM256x9ASTP RAM256x9ASR RAM256x9ASRP RAM256x9SA RAM256xSAP RAM256x9SST RAM256x9SSTP RAM256x9SSR RAM256x9SSRP FIFO256x9AA FIFO256x9AAP FIFO256x9AST FIFO256x9ASTP FIFO256x9ASR FIFO256x9ASRP FIFO256x9SA FIFO256x9SAP FIFO256x9SST FIFO256x9SSTP FIFO256x9SSR FIFO256x9SSRP 22 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s DI <0:8> WADDR <0:7> WRB WBLKB WCLKS WPE SRAM (256 X 9) Sync Write & Sync Read Ports DO <0:8> RADDR <0:7> RDB RBLKB RCLKS RPE DI <0:8> WADDR <0:7> WRB WBLKB WPE SRAM (256 X 9) Async Write & Async Read Ports DO <0:8> RADDR <0:7> RDB RBLKB RPE PARODD PARODD DO <0:8> RADDR <0:7> RDB RBLKB DI <0:8> WADDR <0:7> WRB WBLKB DO <0:8> RADDR <0:7> RDB RBLKB RCLKS RPE DI <0:8> WADDR <0:7> WRB WBLKB WCLKS WPE SRAM (256 X 9) Sync Write & Async Read Ports SRAM (256 X 9) Async Write & Sync Read Ports RPE WPE PARODD Note: PARODD To save area while using embedded memories, the memory blocks contain multiplexers (called DMUX) for each output signal. These DMUX cells do not consume any core logic tiles and connect directly to high speed routing resources between the memory blocks. They are used when memories are cascaded and are automatically inserted by the software tools. Figure 21 * Example SRAM Block Diagrams Table 9 * Memory Block SRAM Interface Signals SRAM Signal Bits In/Out Description Write clock used on synchronization on write side Read clock used on synchronization on read side Read address Read block select (active LOW) Read pulse (active LOW) Write address Write block select (active LOW) Input data bits <0:8>, <8> can be used for parity in Write pulse (active LOW) Output data bits <0:8>, <8> can be used for parity out Read parity error Write parity error Selects odd parity generation/detect when high, even when low WCLKS 1 IN RCLKS 1 IN RADDR<0:7> 8 IN RBLKB 1 IN RDB 1 IN WADDR<0:7> 8 IN WBLKB 1 IN DI<0:8> 9 IN WRB 1 IN DO<0:8> 9 OUT RPE 1 OUT WPE 1 OUT PARODD 1 IN Note: Not all signals shown are used in all modes. v3.0 23 Pr o A S I C P L U S F la s h F a m il y F P GA s DI<0:8> LEVEL<0:7> LGDEP<0:2> WRB WBLKB RDB RBLKB PARODD WCLKS DO <0:8> FIFO (256 X 9) Sync Write & Sync Read Ports WPE RPE FULL EMPTY EQTH GEQTH RESET RCLKS DI <0:8> LEVEL <0:7> LGDEP<0:2> WRB WBLKB RDB RBLKB PARODD WCLKS DO <0:8> FIFO (256 X 9) Sync Write & Async Read Ports WPE RPE FULL EMPTY EQTH GEQTH RESET DI <0:8> LEVEL <0:7> LGDEP<0:2> WRB WBLKB RDB RBLKB PARODD DO <0:8> FIFO (256 X 9) Async Write & Sync Read Ports WPE RPE FULL EMPTY EQTH GEQTH RESET RCLKS DI <0:8> LEVEL <0:7> LGDEP<0:2> WRB WBLKB DO <0:8> RDB RBLKB PARODD FIFO (256 X 9) Async Write & Async Read Ports WPE RPE FULL EMPTY EQTH GEQTH RESET Note: To save area while using embedded memories, the memory blocks contain multiplexers (called DMUX) for each output signal. These DMUX cells do not consume any core logic tiles and connect directly to high speed routing resources between the memory blocks. They are used when memories are cascaded and are automatically inserted by the software tools. Figure 22 * Basic FIFO Block Diagrams Table 10 * Memory Block FIFO Interface Signals FIFO Signal WCLKS RCLKS LEVEL <0:7> RBLKB RDB RESET WBLKB DI<0:8> WRB FULL, EMPTY EQTH, GEQTH DO<0:8> RPE WPE LGDEP <0:2> PARODD Bits 1 1 8 1 1 1 1 9 1 2 2 9 1 1 3 1 In/Out IN IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT IN IN Description Write clock used for synchronization on write side Read clock used for synchronization on read side Direct configuration implements static flag logic Read block select (active LOW) Read pulse (active LOW) Reset for FIFO pointers (active LOW) Write block select (active LOW) Input data bits <0:8>, <8> will be generated if PARGEN is true Write pulse (active LOW) FIFO flags. FULL prevents write and EMPTY prevents read EQTH is true when the FIFO holds the number of words specified by the LEVEL signal. GEQTH is true when the FIFO holds (LEVEL) words or more Output data bits <0:8> Read parity error Write parity error Configures DEPTH of the FIFO to 2 (LGDEP+1) Parity generation/detect - Even when low, odd when high 24 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s Word Width 9 9 9 9 9 9 Word Depth 256 256 88 blocks 256 256 ... 9 256 256 256 9 9 256 256 Figure 23 * APA1000 Memory Block Architecture Word Width 9 Word Depth 256 9 9 9 9 256 256 256 256 256 words x 18 bits, 1 read, 1 write 256 256 256 256 512 words x 18 bits, 1 read, 1 write 256 1,024 words x 9 bits, 1 read, 1 write Total Memory Blocks Used = 10 Total Memory Bits = 23,040 Figure 24 * Example Showing Memories with Different Widths and Depths Word Width 9 Word Depth 9 9 9 9 9 Write Port 9 9 9 Write Port 256 256 256 256 256 256 Read Ports 256 words x 9 bits, 2 read, 1 write 256 256 256 256 Read Ports 512 words x 9 bits, 4 read, 1 write Total Memory Blocks Used = 10 Total Memory Bits = 6,912 Figure 25 * Multiport Memory Usage v3.0 25 Pr o A S I C P L U S F la s h F a m il y F P GA s D es i gn E nv i r on m e nt The ProASICPLUS family of FPGAs is fully supported by both Actel's LiberoTM Integrated Design Environment and Actel's Designer FPGA Development Software. Actel's Designer software provides a comprehensive suite of backend development tools for FPGA development. The Designer software includes timing-driven place and route, a world-class integrated static timing analyzer and constraints editor, a design netlist schematic viewer, and SmartPower, a tool that allows the user to quickly estimate the power consumption in a design. Libero IDE provides an integrated design manager that seamlessly integrates design tools while guiding the user through the design flow, managing all design and log files, and passing necessary design data among tools (Figure 26). Libero IDE includes Synplicity (R) Synplify for Actel, Mentor GraphicsTM ViewDraw for Actel, Actel's own Designer software, Model TechnologyTM ModelSim HDL Simulator, and SynaptiCADTM WaveFormer Lite. ISP The user can generate *.bit or *.stp programming files from the Designer software and can use these files to program a device. ProASICPLUS devices can be programmed in system. For more information on ISP of ProASICPLUS devices, refer to the In-System Programming ProASICPLUS Devices and Performing Internal In-System Programming Using Actel's ProASICPLUS Devices application notes. Prior to being programmed for the first time, the ProASICPLUS device I/Os are inputs with pull-ups. Libero TM IDE Project Manager Design Creation/Verification ACTgen Macro Builder HDL Editor User Testbench Stimulus Generation Functional Simulation Synthesis Libraries Synthesis Design Synthesis and Optimization Simulator Schematic Entry Timing Simulation Design Implementation Timer Static Timing Analyzer and Constraints Editor Compile Optimization and DRC SmartPower Power Analysis PinEdit I/O Assignments Layout Timing Driven Place-and-Route NetlistViewer Schematic Viewer ChipEdit and ChipViewer Placement Editor Fuse or Bitstream Back-Annotate Cross-Probing Programming Silicon Sculptor (Antifuse and Flash Families) System Verification Actel Device Silicon Explorer II (Antifuse and Flash Families) FlashPro (Flash Families) (ProASIC PLUS Family) FlashPro Lite BP Microsystems Programmers Figure 26 * Design Flow 26 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s Pa c ka ge T he r m a l C ha r a ct e r i s t i c s The ProASICPLUS family is available in several package types with a range of pin counts. Actel has selected packages based on high pin count, reliability factors, and superior thermal characteristics. Thermal resistance defines the ability of a package to conduct heat away from the silicon, through the package to the surrounding air. Junction-to-ambient thermal resistance is measured in degrees Celsius/Watt and is represented as Theta ja (ja). The lower the thermal resistance, the more efficiently a package will dissipate heat. A package's maximum allowed power (P) is a function of maximum junction temperature (TJ), maximum ambient operating temperature (TA), and junction-to-ambient Package Type Thin Quad Flat Pack (TQFP) Thin Quad Flat Pack (TQFP) Plastic Quad Flat Pack (PQFP) PQFP with Heatspreader Plastic Ball Grid Array (PBGA) Fine Pitch Ball Grid Array (FBGA) Fine Pitch Ball Grid Array (FBGA) Fine Pitch Ball Grid Array Fine Pitch Ball Grid Array (FBGA)1 (FBGA)2 Pin Count 100 144 208 208 456 144 256 484 484 676 896 1152 thermal resistance ja. Maximum junction temperature is the maximum allowable temperature on the active surface of the IC and is 110 C. P is defined as: TJ - TA P = --------------- ja ja is a function of the rate (in linear feet per minute - lfpm) of airflow in contact with the package. When the estimated power consumption exceeds the maximum allowed power, other means of cooling, such as increasing the airflow rate, must be used. jc 12 11 8 3.8 3 3.8 3.8 3.2 3.2 3.2 2.4 1.8 ja Still Air 37.5 32 30 20 15.6 38.8 25 20 20.5 16.4 13.6 12 ja 300 ft./min. 30 24 23 17 12 26.7 22 15 16.6 11.5 10.3 8.9 Units C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W Fine Pitch Ball Grid Array (FBGA) Fine Pitch Ball Grid Array (FBGA) Fine Pitch Ball Grid Array (FBGA) Notes: 1. Depopulated Array 2. Full Array v3.0 27 Pr o A S I C P L U S F la s h F a m il y F P GA s C al c ul a t i n g T y pi c al Po w er D i ss i pa t i o n ProASICPLUS device power is calculated with both a static and an active component. The active component is a function of both the number of tiles utilized and the system speed. Power dissipation can be calculated using the following formula: Ptotal = Pdc + Pac where: * Pdc = 12.5 mW (Typically 2.5V x 5mA) Pdc includes the static components of: PVDDP + PVDD + PAVDD * Pac = Pclock + Pstorage + Plogic + Pinputs Pmemory + Ppll Poutputs, the I/O component of AC power dissipation, is given by Poutputs = (P4 + (Cload * VDDP2)) * p * Fp where: * P4 = 326 W/MHz is the intrinsic power consumption of an output pad normalized per MHz of the output frequency. This is the total I/O current VDD + VDDP * Cload = the output load * p = the number of outputs * Fp = the average output frequency The input's component of AC power dissipation is given by Pinputs = P8 * q * Fq where: * P8 = 29 W/MHz is the intrinsic power consumption of an input pad normalized per MHz of the input frequency * q = the number of inputs * Fq = the average input frequency Ppll = P9 * Npll where: * P9 = 6.9 mW. This value has been estimated at maximum PLL clock frequency * NPll = number of PLLs used Finally, Pmemory, the memory component of AC power consumption, is given by Pmemory = P6 * Nmemory * Fmemory * Ememory where: * P6 = 175 W/MHz is the average power consumption of a memory block per MHz of the clock * Nmemory = the number of RAM/FIFO blocks (1 block = 256 words * 9 bits) * Fmemory = the clock frequency of the memory * Ememory = the average number of active blocks divided by the total number of blocks (N) of the memory. * Typical values for Ememory would be 1/4 for a 1k x 8,9,16, 32 memory and 1/16 for a 4kx8, 9, 16, and 32 memory * In addition, an application-dependent component to Ememory can be considered. For example, for a 1kx8 memory using only 1 cycle out of 3, Ememory = 1/4*1/3 = 1/12 + Poutputs + Pclock, the clock component of power dissipation, is given by Pclock = (P1 + P2 * R - P7*R2) * Fs where: * P1 = 100 W/MHz is the basic power consumption of the clock tree per MHz of the clock * P2 = 1.3 W/MHz is the incremental power consumption of the clock tree per storage tile - also per MHz of the clock * P7 = 0.00003 W/MHz is a correction factor for highly loaded clock-trees * R = the number of storage tiles clocked by this clock * Fs = the clock frequency Pstorage, the storage-tile (Register) component of AC power dissipation, is given by Pstorage = P5 * ms * Fs where: * P5 = 1.1 W/MHz is the average power consumption of a storage-tile per MHz of its output toggling rate. The maximum output toggling rate is Fs/2 * ms = the number of storage tiles (Register) switching during each Fs cycle * Fs = the clock frequency Plogic, the logic-tile component of AC power dissipation, is given by Plogic = P3 * mc * Fs where: * P3 = 1.4 W/MHz, is the average power consumption of a logic tile per MHz of its output toggling rate. The maximum output toggling rate is Fs/2 * mc = the number of logic tiles switching during each Fs cycle * Fs = the clock frequency 28 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s The following is an APA750 example using a shift register design with 13,440 storage tiles (Register) and 0 logic tiles. This design has one clock at 10 MHz, and 24 outputs toggling at 5 MHz. We then calculate the various components as follows: Pclock * Fs = 10 MHz * R = 13,440 => Pclock = (P1 + P2 * R - P7*R2) * Fs = 124.2 mW Pstorage * ms = 13,440 (in a shift register 100% of storage-tiles are toggling at each clock cycle and Fs = 10 MHz) => Pstorage = P5 * ms * Fs = 147.8 mW Plogic * mc = 0 (no logic tile in this shift-register) => Plogic = 0 mW Poutputs * * * * Cload VDDP p Fp = = = = 40 pF 3.3 V 24 5 MHz => Poutputs = (P4 + Cload * VDDP2) * p * Fp = 87.3 mW Pinputs *q =1 * Fq = 10 MHz => Pinputs = P8 * q * Fq = 0.3 mW Pmemory Nmemory = 0 (no RAM/FIFO in this shift-register) => Pac => 360 mW Ptotal Pdc + Pac = 372 mW (Typical) Pmemory = 0 mW v3.0 29 Pr o A S I C P L U S F la s h F a m il y F P GA s O pe r a t i ng C on d i t i on s Standard and -F parts are the same unless otherwise noted. -F parts are only available as commercial. Abs ol ut e M axim u m Ra ti ngs * Parameter Condition Minimum Maximum Units Supply Voltage Core (VDD) -0.3 3.0 V -0.3 4.0 V Supply Voltage I/O Ring (VDDP) DC Input Voltage -0.3 VDDP + 0.3 V PCI DC Input Voltage -1.0 VDDP + 1.0 V PCI DC Input Clamp Current (absolute) VIN < -1 or VIN= VDDP + 1V 10 mA LVPECL Input Voltage -0.3 VDDP + 0.5 V GND 0 0 V Note: * Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the Recommended Operating Conditions. P rog ra m mi ng , St or age and Oper at in g L i m it s Storage Temperature Operating TJ Max Junction Temperature Product Grade Programming Cycles Program Retention Min. Max. Commercial 100 20 years -55C 110C 110C Industrial 100 20 years -55C 110C 110C Note: This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification is not implied. S uppl y Vol t ages Mode Single Voltage Mixed Voltage VDD 2.5V 2.5V Commercial/Industrial VDDP 2.5V 3.3V Parameter VPP VPN Condition During Programming Normal Operation1 During Programming Normal Operation2 During Programming During Programming Minimum 15.8 0 -13.8 -13.8 Maximum 16.5 16.5 -13.2 0 25 10 VDD GND Units V V V V mA mA V V IPP IPN AVDD VDD AGND GND Notes: 1. Please refer to the "VPP Programming Supply Pin" section on page 60 for more information. 2. Please refer to the "VPN Programming Supply Pin" section on page 61 for more information. Rec om m ende d Op era ti ng Con dit io ns Limits Parameter DC Supply Voltage (2.5V I/Os) DC Supply Voltage (Mixed 2.5V, 3.3V I/Os) Operating Ambient Temperature Range Maximum Operating Junction Temperature Symbol VDD & VDDP VDDP VDD TA TJ Commercial 2.5V 0.2V 3.3V 0.3V 2.5V 0.2V 0C to 70C 110C Industrial 2.5V 0.2V 3.3V 0.3V 2.5V 0.2V -40C to 85C 110C 30 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s DC E le ct ri cal S peci fic at ions ( V D D P = 2. 5V 0.2V) 1 Commercial / Industrial1 , 2 Min. 2.1 2.0 1.7 2.1 1.9 1.7 0.2 0.4 0.7 0.2 0.4 0.7 1.7 -0.3 VDDP + 0.3 0.7 56 0.35 0.45 - 20 10 5.0 5.0 5.0 -10 -10 -120 -100 100 30 10 10 15 25 20 10 100 V V k V A A mA mA mA A A mA Typ. Max. Units Symbol Parameter Output High Voltage High Drive (OB25LPH) Conditions IOH = -6 mA IOH = -12 mA IOH = -24 mA IOH = -3 mA IOH = -6 mA IOH = -8 mA IOL = 8 mA IOL = 15 mA IOL = 24 mA IOL = 4 mA IOL = 8 mA IOL = 15 mA VOH Low Drive (OB25LPL) V Output Low Voltage High Drive (OB25LPH) VOL Low Drive (OB25LPL) V VIH VIL RWEAKPULLUP HYST IIN Input High Voltage Input Low Voltage Weak Pull-up Resistance (OTB25LPU) Input Hysteresis Schmitt Input Current Quiescent Supply Current (standby) Commercial Quiescent Supply Current (standby) Industrial VIN 1.25V See Table 4 on page 11 with pull up (VIN = GND) without pull up (VIN = GND or VDD) Std. VIN = GND3 or VDD -F Std. Std. -F4 6 0.3 -240 -10 IDDQ IDDQ VIN = GND3 or VDD IOZ 3-State Output Leakage Current VOH = GND or VDD Output Short Circuit Current High High Drive (OB25LPH) VIN = VSS VIN = VSS Low Drive (OB25LPL) Output Short Circuit Current Low High Drive (OB25LPH) VIN = VDDP Low Drive (OB25LPL) VIN = VDDP I/O Pad Capacitance Clock Input Pad Capacitance IOSH IOSL CI/O CCLK mA pF pF Notes: 1. All process conditions. Junction Temperature: -40 to +110C. 2. -F parts are only available as commercial. 3. No pull-up resistor. 4. This will not exceed 2mA total per device. v3.0 31 Pr o A S I C P L U S F la s h F a m il y F P GA s DC E le ct ri cal S peci fic at ions ( V D D P = 3. 3V 0.3V an d V D D 2 .5V 0.2V) 1 Commercial / Industrial1,2 Min. 0.9VDDP 2.4 V 0.9VDDP 2.4 2.1 2.0 1.7 V 2.1 2.0 1.7 0.1VDDP 0.4 0.7 V 0.1VDDP 0.4 0.7 0.2 0.4 0.7 V 0.2 0.4 0.7 2 1.7 0.3 0.3 VDDP + 0.3 VDDP + 0.3 0.8 0.7 43 43 -40 10 15 25 20 V Typ. Max. Units Symbol Parameter Output High Voltage 3.3V I/O, High Drive (OB33P) Conditions IOH = -14 mA IOH = -24 mA IOH = -6 mA IOH = -12 mA 3.3V I/O, Low Drive (OB33L) VOH Output High Voltage IOH = -0.1 mA 2.5V I/O, High Drive (OB25H) IOH = -0.5 mA IOH = -3.0 mA IOH = -0.1 mA IOH = -0.5 mA IOH = -1.0 mA IOL = 15 mA IOL = 20 mA IOL = 28 mA IOL = 7 mA IOL = 10 mA IOL = 15 mA 2.5V I/O, Low Drive (OB25L) Output Low Voltage 3.3V I/O, High Drive (OB33P) 3.3V I/O, Low Drive (OB33L) VOL Output Low Voltage IOL = 7 mA 2.5V I/O, High Drive (OB25H) IOL = 14 mA IOL = 28 mA IOL = 5 mA IOL = 10 mA IOL = 15 mA 2.5V I/O, Low Drive (OB25L) Input High Voltage 3.3V LVTTL/LVCMOS 2.5V Mode Input Low Voltage 3.3V LVTTL/LVCMOS VIL 2.5V Mode Weak Pull-up Resistance RWEAKPULLUP (IOB33U) Weak Pull-up Resistance RWEAKPULLUP (IOB25U) IIN IDDQ Input Current Quiescent Supply Current (standby) Commercial Quiescent Supply Current (standby) Industrial VIH V k k A A mA mA mA VIN 1.5V VIN 1.5V with pull up (VIN = GND) without pull up (VIN = GND or VDD) Std. VIN = GND3 or VDD -F Std. 7 7 -300 -10 5.0 5.0 5.0 IDDQ VIN = GND3 or VDD Notes: 1. All process conditions. Junction Temperature: -40 to +110C. 2. -F parts are only available as commercial. 3. No pull-up resistor. 4. This will not exceed 2mA total per device. 32 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s DC E le ct ri cal S peci fic at ions ( V D D P = 3. 3V 0.3V an d V D D 2 .5V 0.2V) 1 (Con ti nued ) Commercial / Industrial1,2 Symbol IOZ Parameter Conditions Std. -F 4 Min. -10 -10 -200 -100 Typ. Max. 10 100 Units A A 3-State Output Leakage Current VOH = GND or VDD Output Short Circuit Current High VIN = GND 3.3V High Drive (OB33P) VIN = GND 3.3V Low Drive (OB33L) VIN = GND 2.5V High Drive (OB25H) VIN = GND 2.5V Low Drive (OB25L) Output Short Circuit Current Low VIN = VDD 3.3V High Drive VIN = VDD 3.3V Low Drive 2.5V High Drive 2.5V Low Drive VIN = VDD VIN = VDD IOSH mA -20 -10 200 100 mA 200 100 10 10 pF pF IOSL CI/O I/O Pad Capacitance CCLK Clock Input Pad Capacitance Notes: 1. All process conditions. Junction Temperature: -40 to +110C. 2. -F parts are only available as commercial. 3. No pull-up resistor. 4. This will not exceed 2mA total per device. DC S pec if i cat ion s (3.3 V P C I Op era ti on) 1 Commercial / Industrial2,3 Symbol VDD VDDP VIH VIL IIPU IIL VOH VOL CIN CCLK Parameter Supply Voltage for Core Supply Voltage for I/O Ring Input High Voltage Input Low Voltage Input Pull-up Voltage4 0 < VIN < VCCI IOUT = -500 A IOUT = 1500 A 5 Std. -F6 Condition Min. 2.3 3.0 0.5VDDP -0.5 0.7VDDP -10 -10 0.9VDDP 0.1VDDP 10 12 10 100 Max. 2.7 3.6 VDDP + 0.5 0.3VDDP Units V V V V V A A V V pF pF Input Leakage Current5 Output High Voltage Output Low Voltage Input Pin Capacitance (except CLK) CLK Pin Capacitance Notes: 1. For PCI operation, use OTB33PH, OB33PH, IOB33PH, IB33, or IB33S macro library cell only. 2. All process conditions. Junction Temperature: -40 to +110C. 3. -F parts are available as commercial only. 4. This specification is guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a floated network. Designers with applications sensitive to static power utilization should ensure that the input buffer is conducting minimum current at this input voltage. 5. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs. 6. The sum of the leakage currents for all inputs shall not exceed 2mA per device. v3.0 33 Pr o A S I C P L U S F la s h F a m il y F P GA s AC Specifications (3.3V PCI Revision 2.2 Operation) Commercial / Industrial Symbol Parameter Condition 0 < VOUT 0.3VCCI* 0.3VCCI VOUT < Switching Current High 0.9VCCI* IOH(AC) 0.7VCCI < VOUT < VCCI* (Test Point) VOUT = 0.7VCC* VCCI > VOUT 0.6VCCI* 0.6VCCI > VOUT > Switching Current Low 0.1VCCI 1 IOL(AC) 0.18VCCI > VOUT > 0* (Test Point) ICL ICH slewR slewF Note: Low Clamp Current High Clamp Current VOUT = 0.18VCC -3 < VIN -1 -25 + (VIN + 1)/0.015 1 1 4 4 VCCI + 4 > VIN VCCI + 1 25 + (VIN - VDDP - 1)/0.015 16VDDP (26.7VOUT) See equation D - page 124 of the PCI Specification document rev. 2.2 38VCCI mA mA mA V/ns V/ns Min. -12VCCI (-17.1 + (VDDP - VOUT)) See equation C - page 124 of the PCI Specification document rev. 2.2 -32VCCI mA mA mA Max. Units mA mA Output Rise Slew Rate 0.2VCCI to 0.6VCCI load* Output Fall Slew Rate 0.6VCCI to 0.2VCCI load* * Refer to the PCI Specification document rev. 2.2. Pad Loading Applicable to the Rising Edge PCI pin 1/2 in. max output buffer 1k 10 pF Pad Loading Applicable to the Falling Edge PCI pin output buffer 1k 10 pF 34 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s T r i s t a t e B uf f e r D e l a y s EN A OTBx A PAD VOL tDLH 50% 50% VOH 50% tDHL 50% EN PAD tENZL 50% VCC 50% 50% VOL PAD 35pF EN 10% PAD GND tENZH 50% 50% VOH 50% 90% Tr i s t a t e B uf f e r D e l a y s ( W or st -C as e C om m er cia l Cond it ion s, V D D P = 3.0 V, V D D = 2 .3V , 35 p F l oad, T J = 70 C) Max tDLH1 Max tDHL2 Max tENZH3 Max tENZL4 Macro Type OTB33PH OTB33PN OTB33PL OTB33LH OTB33LN OTB33LL OTB25HH OTB25HN OTB25HL OTB25LH OTB25LN OTB25LL OTB25LPHH OTB25LPHN OTB25LPHL OTB25LPLH OTB25LPLN Description 3.3V, PCI Output Current, High Slew Rate 3.3V, High Output Current, Nominal Slew Rate 3.3V, High Output Current, Low Slew Rate 3.3V, Low Output Current, High Slew Rate 3.3V, Low Output Current, Nominal Slew Rate 3.3V, Low Output Current, Low Slew Rate 2.5V, High Output Current, High Slew Rate 2.5V, High Output Current, Nominal Slew Rate 2.5V, High Output Current, Low Slew Rate 2.5V, Low Output Current, High Slew Rate 2.5V, Low Output Current, Nominal Slew Rate 2.5V, Low Output Current, Low Slew Rate 2.5V, Low Power, High Output Current, High Slew Rate5 2.5V, Low Power, High Output Current, Nominal Slew Rate5 2.5V, Low Power, High Output Current, Low Slew Rate5 2.5V, Low Power, Low Output Current, High Slew Rate5 2.5V, Low Power, Low Output Current, Nominal Slew Rate5 2.5V, Low Power, Low Output Current, Low Slew Rate5 STD 2.0 2.2 2.5 2.6 2.9 3.0 3.1 3.1 3.1 4.6 4.6 4.6 2.0 2.4 2.9 2.7 3.5 4.0 -F 2.4 2.6 3.0 3.1 3.5 3.6 3.8 3.7 3.7 5.6 5.6 5.6 2.4 2.9 3.5 3.3 4.2 4.8 STD 2.2 2.9 3.2 4.0 4.3 5.6 1.8 2.7 3.9 2.9 3.7 5.1 2.1 3.0 3.2 4.6 4.2 5.3 -F 2.6 3.5 3.9 4.8 5.2 6.7 2.2 3.3 4.7 3.5 4.5 6.1 2.5 3.6 3.8 5.5 5.1 6.4 STD 2.2 2.4 2.7 2.8 3.2 3.3 2.8 2.9 2.9 4.6 4.6 4.5 2.3 2.7 3.1 3.0 3.8 4.2 -F 2.6 2.9 3.3 3.4 3.8 3.9 3.4 3.5 3.5 5.5 5.5 5.4 2.7 3.2 3.8 3.6 4.5 5.1 STD 2.0 2.1 2.8 3.0 4.1 5.5 1.7 2.7 3.8 2.9 3.6 4.8 2.0 2.1 2.7 2.6 3.8 5.1 -F 2.4 2.5 3.4 3.6 4.9 6.6 2.0 3.2 4.6 3.4 4.3 5.8 2.4 2.5 3.2 3.1 4.6 6.1 Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns OTB25LPLL Notes: 1. tDLH=Data-to-Pad HIGH 2. tDHL=Data-to-Pad LOW 3. tENZH=Enable-to-Pad, Z to HIGH 4. tENZL = Enable-to-Pad, Z to LOW 5. Low power I/O work with VDDP=2.5V 10% only. VDDP=2.3V for delays. v3.0 35 Pr o A S I C P L U S F la s h F a m il y F P GA s O ut p u t B uf f e r D e l ay s A A OBx PAD 35pF 50% 50% VOH 50% 50% PAD VOL tDLH tDHL O ut p u t B uf f e r D e l ay s ( W or st -C as e C om m er cia l Cond it ion s, V D D P = 3.0 V, V D D = 2 .3V , 35 p F l oad, T J = 70 C) Max tDLH1 Macro Type OB33PH OB33PN OB33PL OB33LH OB33LN OB33LL OB25HH OB25HN OB25HL OB25LH OB25LN OB25LL OB25LPHH OB25LPHN OB25LPHL OB25LPLH OB25LPLN OB25LPLL Description 3.3V, PCI Output Current, High Slew Rate 3.3V, High Output Current, Nominal Slew Rate 3.3V, High Output Current, Low Slew Rate 3.3V, Low Output Current, High Slew Rate 3.3V, Low Output Current, Nominal Slew Rate 3.3V, Low Output Current, Low Slew Rate 2.5V, High Output Current, High Slew Rate 2.5V, High Output Current, Nominal Slew Rate 2.5V, High Output Current, Low Slew Rate 2.5V, Low Output Current, High Slew Rate 2.5V, Low Output Current, Nominal Slew Rate 2.5V, Low Output Current, Low Slew Rate 2.5V, Low Power, High Output Current, High Slew Rate3 2.5V, Low Power, High Output Current, Nominal Slew Rate3 Rate3 Rate3 Rate3 2.5V, Low Power, High Output Current, Low Slew 2.5V, Low Power, Low Output Current, High Slew 2.5V, Low Power, Low Output Current, Low Slew STD 2.0 2.2 2.5 2.6 2.9 3.0 3.1 3.1 3.1 4.6 4.6 4.6 2.0 2.4 2.9 2.7 3.5 4.0 -F 2.4 2.6 3.0 3.1 3.5 3.6 3.8 3.7 3.7 5.6 5.6 5.6 2.4 2.9 3.5 3.3 4.2 4.8 Max tDHL2 STD 2.2 2.9 3.2 4.0 4.3 5.6 1.8 2.7 3.9 2.9 3.7 5.1 2.1 3.0 3.2 4.6 4.2 4.3 -F 2.6 3.5 3.9 4.8 5.2 6.7 2.2 3.3 4.7 3.5 4.5 6.1 2.6 3.6 3.8 5.5 5.1 6.4 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2.5V, Low Power, Low Output Current, Nominal Slew Rate3 Notes: 1. tDLH = Data-to-Pad HIGH 2. tDHL = Data-to-Pad LOW 3. Low power I/O work with VDDP=2.5V 10% only. VDDP=2.3V for delays. 36 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s I n pu t B uf f er D e l ay s VCC PAD PAD IBx Y Y GND tINYH 50% 50% VCC 50% tINYL 0V 50% I n pu t B uf f er D e l ay s ( W or st -C as e C om m er cia l Cond it ion s, V D D P = 3.0 V, V D D = 2 .3V , T J = 70 C Max. tINYH1 Macro Type IB25 IB25S IB25LP IB25LPS IB33 IB33S Description 2.5V, CMOS Input Levels3, No Pull-up Resistor 2.5V, CMOS Input Levels 2.5V, CMOS Input 2.5V, CMOS Input 3.3V, CMOS Input 3, Max. tINYL2 Std. 0.8 0.8 0.6 0.9 0.6 0.8 -F 1.0 1.0 0.8 1.1 0.7 0.9 Units ns ns ns ns ns ns Std. 0.7 0.7 0.9 0.7 0.4 0.6 -F 0.9 0.9 1.1 0.9 0.5 0.7 No Pull-up Resistor, Schmitt Trigger Low Power Low Power, Schmitt Trigger No Pull-up Resistor, Schmitt Trigger Levels3, Levels3, Levels3, 3.3V, CMOS Input Levels3, No Pull-up Resistor Notes: 1. tINYH = Input Pad-to-Y HIGH 2. tINYL = Input Pad-to-Y LOW 3. LVTTL delays are the same as CMOS delays. 4. For LP Macros, VDDP=2.3V for delays. G l ob al I np ut Bu f f e r D e l ay s ( W or st -C as e C om m er cia l Cond it ion s, V D D P = 3.0 V, V D D = 2 .3V , T J = 70 ) Max. tINYH1 Macro Type Description GL25 GL25S GL25LP GL25LPS GL33 GL33S PECL 2.5V, CMOS Input 2.5V, CMOS Input 2.5V, CMOS Input 3.3V, CMOS Input 3.3V, CMOS Input Levels3, Levels3, Levels3, Levels3, Levels3, No Pull-up Resistor No Pull-up Resistor, Schmitt Trigger Low Power No Pull-up Resistor No Pull-up Resistor, Schmitt Trigger Std. 1.3 1.3 1.1 1.3 1.0 1.0 1.0 -F 1.6 1.6 1.2 1.6 1.2 1.2 1.2 Max. tINYL2 Std. 1.0 1.0 1.0 1.0 1.1 1.1 1.1 -F 1.2 1.2 1.3 1.1 1.3 1.3 1.3 Units ns ns ns ns ns ns ns 2.5V, CMOS Input Levels3, Low Power, Schmitt Trigger PPECL Input Levels Notes: 1. tINYH = Input Pad-to-Y HIGH 2. tINYL = Input Pad-to-Y LOW 3. LVTTL delays are the same as CMOS delays. 4. For LP Macros, VDDP=2.3V for delays. v3.0 37 Pr o A S I C P L U S F la s h F a m il y F P GA s Pr ed i ct ed G l ob a l Ro u t i ng D el a y* ( W or st -C as e C om m er cia l Cond it ion s, V D D P = 3.0 V, V D D = 2 .3V , T J = 70 C ) Max. Parameter tRCKH tRCKL tRCKH Description Input Low to High (fully loaded row) Input High to Low (fully loaded row) Input Low to High (minimally loaded row) Std. 1.1 1.0 0.8 0.8 -F 1.3 1.2 1.0 1.0 Units ns ns ns ns tRCKL Input High to Low (minimally loaded row) Note: * The timing delay difference between tile locations is less than 15ps. G l ob al R o ut i ng S ke w ( W or st -C as e C om m er cia l Cond it ion s, V D D P = 3.0 V, V D D = 2 .3V , T J = 70 C ) Max. Parameter tRCKSWH tRCKSHH Description Maximum Skew Low to High Maximum Skew High to Low Std. 270 270 -F 320 320 Units ps ps 38 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s M od u l e D e l ay s A B C Y A B C 50% 50% 50% 50% 50% 50% Y 50% 50% 50% 50% 50% 50% tDBLH tDALH tDAHL tDBHL tDCLH tDCHL Sa m p l e M a c r oc e l l Li b r a r y L i s t i ng * ( W or st -C as e C om m er cia l Cond it ion s, V D D = 2.3V , T J = 7 0 C) Standard Cell Name NAND2 AND2 NOR3 MUX2L OA21 XOR2 Description 2-Input NAND 2-Input AND 3-Input NOR 2-1 MUX with Active Low Select 2-Input OR into a 2-Input AND 2-Input Exclusive OR Active Low Latch (LH/HL) LH LDL CLK-Q tsetup thold Negative Edge-Triggered D-type Flip-Flop (LH/HL) LH DFFL CLK-Q tsetup thold Note: HL 0.9 0.8 0.6 0.0 1.1 1.0 HL 0.9 0.8 0.7 0.1 1.1 0.9 Maximu m 0.5 0.4 0.8 0.5 0.8 0.6 Minimum Maximu m 0.6 0.5 1.0 0.6 1.0 0.8 -F Minimum Units ns ns ns ns ns ns ns 0.8 0.2 ns 0.7 0.0 *Intrinsic delays have a variable component, coupled to the input slope of the signal. These numbers assume an input slope typical of local interconnect. v3.0 39 Pr o A S I C P L U S F la s h F a m il y F P GA s Recommended Operating Conditions Limits Parameter Maximum Clock Frequency* Maximum RAM Frequency* Maximum Rise/Fall Time on Inputs* * Schmitt Mode * Non-schmitt Mode Maximum LVPECL Frequency* Maximum tCK Frequency (JTAG) Note: *-F parts will be 20% slower than standard commercial devices. tCK tR/tF tR/tF 100 ns 10 ns 180 MHz 10 MHz Symbol fCLOCK fRAM Commercial/Industrial 180 MHz 150 MHz Slew Rates Measured at C = 30pF, Nominal Power Supplies and 25C Type OB33PH OB33PN OB33PL OB33LH OB33LN OB33LL OB25HH OB25HN OB25HL OB25LH OB25LN OB25LL OB25LPHH OB25LPHN OB25LPHL OB25LPLH OB25LPLN OB25LPLL Note: Trig. Level 10%-90% 10%-90% 10%-90% 10%-90% 10%-90% 10%-90% 20%-60% 20%-60% 20%-60% 20%-60% 20%-60% 20%-60% 10%-90% 10%-90% 10%-90% 10%-90% 10%-90% 10%-90% Rising Edge (nS) 1.60 1.57 1.57 3.80 4.19 5.49 3.31 3.20 3.27 8.41 8.54 8.50 1.55 1.70 1.97 3.57 4.65 5.52 Slew Rate (V/ns) 1.65 1.68 1.68 0.70 0.63 0.48 0.30 0.32 0.31 0.12 0.12 0.12 1.29 1.18 1.02 0.56 0.43 0.36 Falling Edge (nS) 1.65 3.32 1.99 4.84 3.37 2.98 0.75 0.77 0.77 1.38 1.15 1.19 1.56 2.08 2.09 3.93 3.28 3.44 Slew Rate (V/ns) 1.60 0.80 1.32 0.55 0.78 0.89 1.33 1.30 1.30 0.72 0.87 0.84 1.28 0.96 0.96 0.51 0.61 0.58 PCI Mode Yes No No No No No No No No No No No No No No No No No Standard and -F parts. 40 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s Em b e dd ed M e m or y S pe ci f i ca t i o ns This section discusses ProASICPLUS SRAM/FIFO embedded memory and its interface signals, including timing diagrams that show the relationships of signals as they pertain to single embedded memory blocks (Table 11). Table 8 on page 22 shows basic SRAM and FIFO configurations. Simultaneous Read and Write to the same location must be done with care. On such accesses the DI bus is output to the DO bus. Enclosed Timing Diagrams--SRAM Mode: * Synchronous SRAM Read, Access Timed Output Strobe (Synchronous Transparent) * Synchronous SRAM Read, Pipeline Mode Outputs (Synchronous Pipelined) * Asynchronous SRAM Write * Asynchronous SRAM Read, Address Controlled, RDB=0 * Asynchronous SRAM Read, RDB Controlled * Synchronous SRAM Write * Embedded Memory Specifications Table 11 * Memory Block SRAM Interface Signals SRAM Signal Bits In/Out Description WCLKS 1 IN RCLKS 1 IN RADDR<0:7> 8 IN RBLKB 1 IN RDB 1 IN WADDR<0:7> 8 IN WBLKB 1 IN DI<0:8> 9 IN WRB 1 IN DO<0:8> 9 OUT RPE 1 OUT WPE 1 OUT PARODD 1 IN Note: Not all signals shown are used in all modes. The difference between synchronous transparent and pipeline modes is the timing of all the output signals from the memory. In transparent mode, the outputs will change within the same clock cycle to reflect the data requested by the currently valid access to the memory. If clock cycles are short (high clock speed), the data requires most of the clock cycle to change to valid values (stable signals). Processing of this data in the same clock cycle is nearly impossible. Most designers add registers at all outputs of the memory to push the data processing into the next clock cycle. An entire clock cycle can then be used to process the data. To simplify use of this memory setup, suitable registers have been implemented as part of the memory primitive and are available to the user in the synchronous pipeline mode. In this mode, the output signals will change shortly after the second rising edge, following the initiation of the read access. Write clock used on synchronization on write side Read clock used on synchronization on read side Read address True read block select (active LOW) True read pulse (active LOW) Write address Write block select (active LOW) Input data bits <0:8>, <8> can be used for parity in Negative true write pulse Output data bits <0:8>, <8> can be used for parity out Read parity error (active HIGH) Write parity error (active HIGH) Selects odd parity generation/detect when high, even when low v3.0 41 Pr o A S I C P L U S F la s h F a m il y F P GA s Synchronous SRAM Read, Access Timed Output Strobe (Synchronous Transparent) RCLKS Cycle Start RBD, RBLKB RADDR New Valid Address DO Old Data Out New Valid Data Out RPE tRACS tRDCS tRDCH tRACH tOCH tRPCH tCMH tOCA tRPCA tCCYC Note: The plot shows the normal operation status. tCML T J = 0 C t o 11 0 C; V D D = 2 .3V t o 2.7V Symbol txxx CCYC CMH CML OCA OCH RACH RACS RDCH RDCS RPCA RPCH Note: Description Cycle time Clock high phase Clock low phase New DO access from RCLKS Old DO valid from RCLKS RADDR hold from RCLKS RADDR setup to RCLKS RDB hold from RCLKS RDB setup to RCLKS New RPE access from RCLKS Old RPE valid from RCLKS Min. 7.5 3.0 3.0 7.5 Max. Units ns ns ns ns Notes 3.0 0.5 1.0 0.5 1.0 9.5 3.0 ns ns ns ns ns ns ns -F speed grade devices are 20% slower than the standard numbers. 42 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s Synchronous SRAM Read, Pipeline Mode Outputs (Synchronous Pipelined) RCLKS Cycle Start RDB, RBLKB RADDR New Valid Address DO Old Data Out New Valid Data Out RPE Old RPE Out New RPE Out tRACS tRACH tRDCH tRDCS tCMH tCCYC Note: The plot shows the normal operation status. tOCA tRPCH tOCH tRPCA tCML T J = 0 C t o 11 0 C; V D D = 2 .3V t o 2.7V Symbol txxx CCYC CMH CML OCA OCH RACH RACS RDCH RDCS RPCA RPCH Note: Description Cycle time Clock high phase Clock low phase New DO access from RCLKS Old DO valid from RCLKS RADDR hold from RCLKS RADDR setup to RCLKS RDB hold from RCLKS RDB setup to RCLKS New RPE access from RCLKS Old RPE valid from RCLKS Min. 7.5 3.0 3.0 2.0 Max. Units ns ns ns ns Notes 0.75 0.5 1.0 0.5 1.0 4.0 1.0 ns ns ns ns ns ns ns -F speed grade devices are 20% slower than the standard numbers. v3.0 43 Pr o A S I C P L U S F la s h F a m il y F P GA s Asynchronous SRAM Write WADDR WRB, WBLKB DI WPE tAWRS tAWRH tDWRH tWPDA tDWRS tWRML tWRCYC Note: The plot shows the normal operation status. tWPDH tWRMH T J = 0 C t o 11 0 C; V D D = 2 .3V t o 2.7V Symbol txxx AWRH AWRS DWRH DWRS DWRS WPDA WPDH WRCYC WRMH WRML Note: Description WADDR hold from WB WADDR setup to WB DI hold from WB DI setup to WB DI setup to WB WPE access from DI WPE hold from DI Cycle time WB high phase WB low phase Min. 1.0 0.5 1.5 0.5 2.5 3.0 Max. Units ns ns ns ns ns ns Notes PARGEN is inactive PARGEN is active WPE is invalid while PARGEN is active 1.0 7.5 3.0 3.0 ns ns ns ns Inactive Active -F speed grade devices are 20% slower than the standard numbers. 44 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s Asynchronous SRAM Read, Address Controlled, RDB=0 RADDR DO RPE tOAH tRPAH tOAA tRPAA tACYC Note: The plot shows the normal operation status. T J = 0 C t o 11 0 C; V D D = 2 .3V t o 2.7V Symbol txxx Description ACYC OAA OAH RPAA RPAH Note: Read cycle time New DO access from RADDR stable Old DO hold from RADDR stable New RPE access from RADDR stable Old RPE hold from RADDR stable Min. 7.5 7.5 Max. Units ns ns Notes 3.0 10.0 3.0 ns ns ns -F speed grade devices are 20% slower than the standard numbers. v3.0 45 Pr o A S I C P L U S F la s h F a m il y F P GA s Asynchronous SRAM Read, RDB Controlled RB=(RDB+RBLKB) DO RPE tORDH tRPRDH tORDA tRPRDA tRDML tRDCYC Note: The plot shows the normal operation status. tRDMH T J = 0 C t o 1 10 C; V D D = 2 .3V t o 2.7V Symbol txxx ORDA ORDH RDCYC RDMH RDML RPRDA RPRDH Note: Description New DO access from RB Old DO valid from RB Read cycle time RB high phase RB low phase New RPE access from RB Old RPE valid from RB Min. 7.5 Max. Units ns Notes 3.0 7.5 3.0 3.0 9.5 3.0 ns ns ns ns ns ns Inactive setup to new cycle Active -F speed grade devices are 20% slower than the standard numbers. 46 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s Synchronous SRAM Write WCLKS Cycle Start WRB, WBLKB WADDR, DI WPE tWRCH, tWBCH tWRCS, tWBCS tDCS, tWDCS tWPCH tDCH, tWACH tWPCA tCMH tCCYC Note: The plot shows the normal operation status. tCML T J = 0 C t o 11 0 C; V D D = 2 .3V t o 2.7V Symbol txxx CCYC CMH CML DCH DCS WACH WDCS WPCA WPCH WRCH, WBCH WRCS, WBCS Description Cycle time Clock high phase Clock low phase DI hold from WCLKS DI setup to WCLKS WADDR hold from WCLKS WADDR setup to WCLKS New WPE access from WCLKS Old WPE valid from WCLKS WRB & WBLKB hold from WCLKS WRB & WBLKB setup to WCLKS Min. 7.5 3.0 3.0 0.5 1.0 0.5 1.0 3.0 Max. Units ns ns ns ns ns ns ns ns Notes WPE is invalid while PARGEN is active 0.5 0.5 1.0 ns ns ns Notes: 1. On simultaneous read and write accesses to the same location DI is output to DO. 2. -F speed grade devices are 20% slower than the standard numbers. v3.0 47 Pr o A S I C P L U S F la s h F a m il y F P GA s Synchronous Write and Read to the Same Location t CCYC t CMH RCLKS t CML DO Last Cycle Data New Data* WCLKS t WCLKRCLKH t WCLKRCLKS t OCH t OCA * New data is read if WCLKS occurs before setup time. The data stored is read if WCLKS occurs after hold time. Note: The plot shows the normal operation status. T J = 0 C t o 11 0 C; V D D = 2 .3V t o 2.7V Symbol txxx CCYC CMH CML WCLKRCLKS WCLKRCLKH OCH OCA Description Cycle time Clock high phase Clock low phase WCLKS to RCLKS setup time WCLKS to RCLKS hold time Old DO valid from RCLKS New DO valid from RCLKS Min. 7.5 3.0 3.0 - 0.1 Max. Units ns ns ns ns Notes 7.0 3.0 7.5 ns ns ns OCA/OCH displayed for Access Timed Output Notes: 1. This behavior is valid for Access Timed Output and Pipelined Mode Output. The table shows the timings of an Access Timed Output. 2. During synchronous write and synchronous read access to the same location, the new write data will be read out if the active write clock edge occurs before or at the same time as the active read clock edge. The negative setup time insures this behavior for WCLKS and RCLKS driven by the same design signal. 3. If WCLKS changes after the hold time, the data will be read. 4. A setup or hold time violation will result in unknown output data. 5. -F speed grade devices are 20% slower than the standard numbers. 48 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s Asynchronous Write and Synchronous Read to the Same Location t CMH RCLKS t CML DO Last Cycle Data New Data* WB = {WRB + WBLKB} DI t WRCKS t BRCLKH t OCH t OCA t DWRRCLKS t CCYC * New data is read if WB occurs before setup time. The stored data is read if WB occurs after hold time. t DWRH Note: The plot shows the normal operation status. T J = 0 C t o 11 0 C; V D D = 2 .3V t o 2.7V Symbol txxx CCYC CMH CML WBRCLKS WBRCLKH OCH OCA DWRRCLKS DWRH Description Cycle time Clock high phase Clock low phase WB to RCLKS setup time WB to RCLKS hold time Old DO valid from RCLKS New DO valid from RCLKS DI to RCLKS setup time DI to WB hold time Min. 7.5 3.0 3.0 -0.1 Max. Units ns ns ns ns Notes 7.0 3.0 7.5 0 1.5 ns ns ns ns ns OCA/OCH displayed for Access Timed Output Notes: 1. This behavior is valid for Access Timed Output and Pipelined Mode Output. The table shows the timings of an Access Timed Output. 2. In asynchronous write and synchronous read access to the same location, the new write data will be read out if the active write signal edge occurs before or at the same time as the active read clock edge. If WB changes to low after hold time, the data will be read. 3. A setup or hold time violation will result in unknown output data. 4. -F speed grade devices are 20% slower than the standard numbers. v3.0 49 Pr o A S I C P L U S F la s h F a m il y F P GA s Asynchronous Write and Read to the Same Location RB, RADDR DO OLD NEW NEWER WB = {WRB+WBLKB} t ORDA t ORDH t RAWRS t OWRA t OWRH t RAWRH Note: The plot shows the normal operation status. T J = 0 C to 11 0C ; V D D = 2. 3V t o 2 .7V Symbol txxx ORDA ORDH OWRA OWRH RAWRS RAWRH Description New DO access from RB Old DO valid from RB New DO access from WB Old DO valid from WB RB or RADDR from WB RB or RADDR from WB Min. 7.5 Max. Units ns Notes 3.0 3.0 0.5 5.0 5.0 ns ns ns ns ns Notes: 1. During an asynchronous read cycle, each write operation (synchronous or asynchronous) to the same location will automatically trigger a read operation which updates the read data. 2. Violation or RAWRS will disturb access to the OLD data. 3. Violation of RAWRH will disturb access to the NEWER data. 4. -F speed grade devices are 20% slower than the standard numbers. 50 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s Synchronous Write and Asynchronous Read to the Same Location RB, RADDR DO OLD NEW NEWER WCLKS t ORDA t ORDH t OWRA t OWRH t RAWCLKS t RAWCLKH Note: The plot shows the normal operation status. T J = 0 C t o 11 0 C; V D D = 2 .3V t o 2.7V Symbol txxx ORDA ORDH OWRA OWRH RAWCLKS RAWCLKH Description New DO access from RB Old DO valid from RB New DO access from WCLKS Old DO valid from WCLKS RB or RADDR from WCLKS RB or RADDR from WCLKS Min. 7.5 Max. Units ns Notes 3.0 3.0 0.5 5.0 5.0 ns ns ns ns ns Notes: 1. During an asynchronous read cycle, each write operation (synchronous or asynchronous) to the same location will automatically trigger a read operation which updates the read data. 2. Violation of RAWCLKS will disturb access to OLD data. 3. Violation of RAWCLKH will disturb access to NEWER data. 4. -F speed grade devices are 20% slower than the standard numbers. v3.0 51 Pr o A S I C P L U S F la s h F a m il y F P GA s Asynchronous FIFO Full and Empty Transitions The asynchronous FIFO accepts writes and reads while not full or not empty. When the FIFO is full, all writes are inhibited. Conversely, when the FIFO is empty, all reads are inhibited. A problem is created if the FIFO is written during the transition out of full to not full or read during the transition out of empty to not empty. The exact time at which the write or read operation changes from inhibited to accepted after the read (write) signal which causes the transition from full or empty to not full or not empty is indeterminate. This indeterminate period starts 1 ns after the RB (WB) transition, which deactivates full or not empty and ends 3 ns after the RB (WB) transition for slow cycles. For fast cycles, the indeterminate period ends 3 ns (7.5 ns - RDL (WRL)) after the RB (WB) transition, whichever is later (Table 12). The timing diagram for write is shown in Figure 27 on page 53. The timing diagram for read is shown in Figure 28 on page 53. For basic SRAM configurations, see Table 9 on page 23. Enclosed Timing Diagrams - FIFO Mode: * Asynchronous FIFO Read * Asynchronous FIFO Write * Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent) * Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined) * Synchronous FIFO Write * FIFO Reset Table 12 * Memory Block FIFO Interface Signals FIFO Signal WCLKS RCLKS LEVEL <0:7>* RBLKB RDB RESET WBLKB DI<0:8> WRB FULL, EMPTY EQTH, GEQTH DO<0:8> RPE WPE LGDEP <0:2> PARODD Note: Bits 1 1 8 1 1 1 1 9 1 2 2 9 1 1 3 1 In/Out IN IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT IN IN Description Write clock used for synchronization on write side Read clock used for synchronization on read side Direct configuration implements static flag logic Read block select (active LOW) Read pulse (active LOW) Reset for FIFO pointers (active LOW) Write block select (active LOW) Input data bits <0:8>, <8> will be generated if PARGEN is true Write pulse (active LOW) FIFO flags. FULL prevents write and EMPTY prevents read EQTH is true when the FIFO holds the number of words specified by the LEVEL signal. GEQTH is true when the FIFO holds (LEVEL) words or more Output data bits <0:8> Read parity error (active HIGH) Write parity error (active HIGH) Configures DEPTH of the FIFO to 2 (LGDEP+1) Selects odd parity generation/detect when high, even when low *LEVEL is always eight bits (0000.0000, 0000.0001). That means for values of DEPTH greater than 256, not all values will be possible, e.g. for DEPTH=512, the LEVEL can only have the values 2, 4, . . ., 512. The LEVEL signal circuit will generate signals that indicate whether the FIFO is exactly filled to the value of LEVEL (EQTH) or filled equal or higher (GEQTH) than the specified LEVEL. Since counting starts at 0, EQTH will become true when the FIFO holds (LEVEL+1) words for 512-bit FIFOs. 52 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s FULL RB Write cycle Write inhibited Write accepted 1 ns 3 ns WB Note: -F speed grade devices are 20% slower than the standard numbers. Figure 27 * Write Timing Diagram EMPTY WB Read cycle Read inhibited Read accepted 1 ns 3 ns RB Note: -F speed grade devices are 20% slower than the standard numbers. Figure 28 * Read Timing Diagram v3.0 53 Pr o A S I C P L U S F la s h F a m il y F P GA s Asynchronous FIFO Read tRDL Cycle Start RB=(RDB+RBLKB) tRDH RDATA (Empty inhibits read) RPE WB EMPTY FULL EQTH, GETH tRDWRS tORDH tRPRDH tORDA tRPRDA tRDL tRDH tTHRDH tTHRDA tERDH, tFRDH tERDA, tFRDA Note: The plot shows the normal operation status. T J = 0C to 110C; V DD = 2.3V to 2.7V Symbol txxx ERDH, FRDH, THRDH ERDA FRDA ORDA ORDH RDCYC RDWRS Description Old EMPTY, FULL, EQTH, & GETH valid hold time from RB New EMPTY access from RB FULL access from RB New DO access from RB Old DO valid from RB Read cycle time WB , clearing EMPTY, setup to RB RB high phase RB low phase New RPE access from RB Old RPE valid from RB EQTH or GETH access from RB Min. Max. 0.5 Units ns Notes Empty/full/thresh are invalid from the end of hold until the new access is complete 3.01 3.01 7.5 3.0 7.5 3.02 1.0 ns ns ns ns ns ns ns ns ns ns ns ns Enabling the read operation Inhibiting the read operation Inactive Active RDH 3.0 RDL 3.0 RPRDA 9.5 RPRDH THRDA 4.5 Notes: 1. At fast cycles, ERDA and FRDA = MAX (7.5 ns - RDL), 3.0 ns. 2. At fast cycles, RDWRS (for enabling read) = MAX (7.5 ns - WRL), 3.0 ns. 3. -F speed grade devices are 20% slower than the standard numbers. 4.0 54 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s Asynchronous FIFO Write Cycle Start WB=(WRB+WBLKB) WDATA (Full inhibits write) WPE RB FULL EMPTY EQTH, GETH tWRRDS tWPDA tDWRS tEWRH, tFWRH tEWRA, tFWRA tTHWRH tTHWRA tWRL tWRCYC tWRH tDWRH tWPDH Note: The plot shows the normal operation status. T J = 0C to 110C; V DD = 2.3V to 2.7V Symbol txxx DWRH DWRS DWRS EWRH, FWRH, THWRH EWRA FWRA THWRA WPDA WPDH WRCYC WRRDS WRH Description DI hold from WB DI setup to WB DI setup to WB Old EMPTY, FULL, EQTH, & GETH valid hold time after WB EMPTY access from WB New FULL access from WB EQTH or GETH access from WB WPE access from DI WPE hold from DI Cycle time RB , clearing FULL, setup to WB WB high phase Min. 1.5 0.5 2.5 Max. Units ns ns ns Notes PARGEN is inactive PARGEN is active Empty/full/thresh are invalid from the end of hold until the new access is complete 0.5 ns 3.01 3.01 4.5 3.0 1.0 7.5 3.02 1.0 3.0 ns ns ns ns ns ns ns ns ns Enabling the write operation Inhibiting the write operation Inactive Active WPE is invalid while PARGEN is active WRL WB low phase 3.0 Notes: 1. At fast cycles, EWRA, FWRA = MAX (7.5 ns - WRL), 3.0 ns. 2. At fast cycles, WRRDS (for enabling write) = MAX (7.5 ns - RDL), 3.0 ns. 3. -F speed grade devices are 20% slower than the standard numbers. v3.0 55 Pr o A S I C P L U S F la s h F a m il y F P GA s Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent) RCLK Cycle Start RDB RDATA Old Data Out New Valid Data Out (Empty Inhibits Read) RPE EMPTY FULL EQTH, GETH tRDCH tRDCS tOCH tRPCH tOCA tRPCA tCMH tCCYC tCML tTHCBH tHCBA tECBH, tFCBH tECBA, tFCBA Note: The plot shows the normal operation status. T J = 0C to 110C; V DD = 2.3V to 2.7V Symbol txxx Description Min. Max. Units ns ns ns ns ns Notes CCYC Cycle time 7.5 CMH Clock high phase 3.0 CML Clock low phase 3.0 ECBA New EMPTY access from RCLKS 3.01 FCBA FULL access from RCLKS 3.01 ECBH, Old EMPTY, FULL, EQTH, & GETH valid FCBH, hold time from RCLKS THCBH OCA New DO access from RCLKS 7.5 OCH Old DO valid from RCLKS RDCH RDB hold from RCLKS 0.5 RDCS RDB setup to RCLKS 1.0 RPCA New RPE access from RCLKS 9.5 RPCH Old RPE valid from RCLKS HCBA EQTH or GETH access from RCLKS 4.5 Notes: 1. At fast cycles, ECBA and FCBA = MAX (7.5 ns - CMH), 3.0 ns. 2. -F speed grade devices are 20% slower than the standard numbers. 1.0 ns ns ns ns ns ns ns ns Empty/full/thresh are invalid from the end of hold until the new access is complete 3.0 3.0 56 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined) RCLK Cycle Start RDB RDATA Old Data Out New Valid Data Out RPE Old RPE Out New RPE Out EMPTY FULL EQTH, GETH tECBH, tFCBH tRDCH tRDCS tTHCBH tHCBA tRPCA tCMH tCCYC tCML tOCA tECBA, tFCBA tRPCH tOCH Note: The plot shows the normal operation status. T J = 0C to 110C; V DD = 2.3V to 2.7V Symbol txxx CCYC CMH CML ECBA FCBA Description Cycle time Clock high phase Clock low phase New EMPTY access from RCLKS FULL access from RCLKS Min. 7.5 3.0 3.0 3.01 3.01 Max. Units ns ns ns ns ns Notes ECBH, FCBH, Old EMPTY, FULL, EQTH, & GETH valid THCBH hold time from RCLKS OCA New DO access from RCLKS 2.0 OCH Old DO valid from RCLKS RDCH RDB hold from RCLKS 0.5 RDCS RDB setup to RCLKS 1.0 RPCA New RPE access from RCLKS 4.0 RPCH Old RPE valid from RCLKS HCBA EQTH or GETH access from RCLKS 4.5 Notes: 1. At fast cycles, ECBA and FCBA = MAX (7.5 ns - CMS), 3.0 ns. 2. -F speed grade devices are 20% slower than the standard numbers. 1.0 ns ns ns ns ns ns ns ns Empty/full/thresh are invalid from the end of hold until the new access is complete 0.75 1.0 v3.0 57 Pr o A S I C P L U S F la s h F a m il y F P GA s Synchronous FIFO Write WCLKS Cycle Start WRB, WBLKB (Full Inhibits Write) DI WPE FULL EMPTY EQTH, GETH tWRCH, tWBCH tWRCS, tWBCS tDCS tWPCH tDCH tWPCA tCMH tCCYC tCML tHCBA tECBH, tFCBH tECBA, tFCBA tHCBH Note: The plot shows the normal operation status. T J = 0C to 110C; V DD = 2.3V to 2.7V Symbol txxx Description Min. Max. Units ns ns ns ns ns ns ns ns Notes CCYC Cycle time 7.5 CMH Clock high phase 3.0 CML Clock low phase 3.0 DCH DI hold from WCLKS 0.5 DCS DI setup to WCLKS 1.0 FCBA New FULL access from WCLKS 3.01 ECBA EMPTY access from WCLKS 3.01 ECBH, Old EMPTY, FULL, EQTH, & GETH valid FCBH, hold time from WCLKS HCBH HCBA EQTH or GETH access from WCLKS 4.5 WPCA New WPE access from WCLKS 3.0 WPCH Old WPE valid from WCLKS WRCH, WRB & WBLKB hold from WCLKS 0.5 WBCH WRCS, WRB & WBLKB setup to WCLKS 1.0 WBCS Notes: 1. At fast cycles, ECBA and FCBA = MAX (7.5 ns - CMH), 3.0 ns. 2. -F speed grade devices are 20% slower than the standard numbers. 1.0 Empty/full/thresh are invalid from the end of hold until the new access is complete WPE is invalid while PARGEN is active 0.5 ns ns ns ns ns 58 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s FIFO Reset RESETB Cycle Start WB* WCLKS, RCLKS Cycle Start FULL EMPTY EQTH, GETH tCBRSS tERSA, tFRSA tTHRSA *WB = WRB + WBLRB tRSL tCBRSH tWBRSH tWBRSS Note: *The plot shows the normal operation status. T J = 0 C t o 11 0 C; V D D = 2 .3V t o 2.7V Symbol txxx CBRSH CBRSS ERSA FRSA RSL THRSA WBRSH WBRSS Note: Description WCLKS or RCLKS hold from RESETB WCLKS or RCLKS setup to RESETB New EMPTY access from RESETB FULL access from RESETB RESETB low phase EQTH or GETH access from RESETB WB hold from RESETB WB setup to RESETB Min. 1.5 1.5 3.0 3.0 7.5 4.5 1.5 1.5 Max. Units ns ns ns ns ns ns ns ns Notes Synchronous mode only Synchronous mode only Asynchronous mode only Asynchronous mode only -F speed grade devices are 20% slower than the standard numbers. v3.0 59 Pr o A S I C P L U S F la s h F a m il y F P GA s Pi n D es c r i pt i on U se r P in s I/O User Input/Output TDI Test Data In The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output signal levels are compatible with standard LVTTL and LVCMOS specifications. Unused I/O pins are configured as inputs with pull-up resistors. NC No Connect Serial input for boundary scan. A dedicated pull-up resistor is included to pull this pin high when not being driven. TDO Test Data Out Serial output for boundary scan. Actel recommends adding a nominal 20k pull-up resistor to this pin. TRST Test Reset Input To maintain compatibility with other Actel ProASICPLUS products, it is recommended that this pin not be connected to the circuitry on the board. GL Global Pin Asynchronous, active low input pin for resetting boundary-scan circuitry. This pin has an internal pull-up resistor. S pec ial Fu nct ion P in s RCK Running Clock Low skew input pin for clock or other global signals. This pin can be configured with an internal pull-up resistor. When it is not connected to the global network or the clock conditioning circuit, it can be configured and used as a normal I/O. GLMX Global Multiplexing Pin A free running clock is needed during programming if the programmer cannot guarantee that TCK will be uninterrupted. If not used, this pin has an internal pull-up and can be left floating. NPECL User Negative Input Low skew input pin for clock or other global signals. This pin can be used in one of two special ways: (Please see Actel's ProASICPLUS Clock Conditioning Circuits application note for details). 1. When the external feedback option is selected for the PLL block, this pin is routed as the external feedback source to the clock conditioning circuit. 2. In applications where two different signals access the same global net (but at different times) through the use of GLMXx and GLMXLx macros, this pin will be fixed as one of the source pins. This pin can be configured with an internal pull-up resistor. When it is not connected to the global network or the clock conditioning circuit, it can be configured and used as any normal I/O. If not used, a global will be configured as an input with pull-up. Ded ica ted P in s GND Ground Provides high speed clock or data signals to the PLL block. If unused, leave the pin unconnected. PPECL User Positive Input Provides high speed clock or data signals to the PLL block. If unused, leave the pin unconnected. AVDD PLL Power Supply Analog VDD should be VDD (core voltage) 2.5V (nominal) and be decoupled from GND with suitable decoupling capacitors to reduce noise. For more information, refer to Actel's Using ProASICPLUS Clock Conditioning Circuits application note. If the PLLs or clock conditioning circuitry are not used in a design, AVDD should be tied high (2.5V normal). AGND PLL Power Ground Analog GND should be 0V and be decoupled from GND with suitable decoupling capacitors to reduce noise. For more information, refer to Actel's ProASICPLUS Clock Conditioning Circuits application note. If the PLLs or clock conditioning circuitry are not used in a design, AGND should be tied to GND. VPP Programming Supply Pin Common ground supply voltage. V DD V DDP TMS Logic Array Power Supply Pin 2.5V supply voltage. I/O Pad Power Supply Pin 2.5V or 3.3V supply voltage. Test Mode Select The TMS pin controls the use of boundary-scan circuitry. This pin has an internal pull-up resistor. TCK Test Clock This pin may be connected to any voltage between GND and 16.5V during normal operation, or it can be left unconnected.2 For information on using this pin during programming, see the Performing Internal In-System Programming Using Actel's ProASICPLUS Devices application note. Actel recommends floating the pin or connecting it to VDDP. Clock input pin for boundary scan (maximum 10 MHz). Actel recommends adding a nominal 20k pull-up resistor to this pin. 2. There is a nominal 40k pull-up resistor on VPP. 60 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s V PN Programming Supply Pin This pin may be connected to any voltage between GND and -13.8V during normal operation, or it can be left unconnected.3 For information on using this pin during programming, see the Performing Internal In-System Programming Using Actel's ProASICPLUS Devices application note. Actel recommends floating the pin or connecting it to GND. R ec om m e n de d D e si g n Pr a c t i ce f o r V PN / V P P capacitance between the VPP and VPN pins and GND (using the shortest paths possible). Without sufficient bypass capacitance to counteract the inductance, the VPP and VPN pins may incur a voltage spike beyond the voltage that the device can withstand. This issue applies to all programming configurations. The power supply voltage limits are defined in the "Supply Voltages" table on page 30. The solution prevents spikes from damaging the ProASICPLUS devices. Bypass capacitors are required for the VPP and VPN pads. Use a 0.01 F to 0.1 F ceramic capacitor with a 25V or greater rating. To filter low-frequency noise (decoupling), use a 4.7 F (low ESR, <1 <, tantalum, 25V or greater rating) capacitor. The capacitors should be located as close to the device pins as possible (within 2.5cm is desirable). The smaller, high-frequency capacitor should be placed closer to the device pins than the larger low-frequency capacitor. The same dual capacitor circuit should be used on both the VPP and VPN pins (Figure 29). Bypass capacitors are required from VPP to GND and VPN to GND for all ProASICPLUS devices during programming. During the erase cycle, ProASICPLUS devices may have current surges on the VPP and VPN power supplies. The only way to maintain the integrity of the power distribution to the ProASICPLUS device during these current surges is to counteract the inductance of the finite length conductors that distribute the power to the device. This can be accomplished by providing a sufficient amount of bypass 3. There is a nominal 40k pull-down resistor on VPN. 2.5cm V PP +_ 0.1F or 0.01F 4.7F + Programming Header or Supplies _+ 0.1F or 0.01F 4.7F + Actel PLUS ProASIC Device V PN Figure 29 * ProASICPLUS VPP and VPN Capacitor Requirements v3.0 61 Pr o A S I C P L U S F la s h F a m il y F P GA s Pa c ka ge P i n A s si g nm e n t s 100- P in T Q FP 100 1 100-Pin TQFP 62 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 100- P in T Q FP 100- P in T Q FP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 APA075 Function GND I/O I/O I/O I/O I/O I/O I/O GND I/O (GLMX1) GL1 AGND NPECL1 AVDD PPECL1 (I/P) GL2 VDD I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD GND VDDP GND I/O I/O APA150 Function GND I/O I/O I/O I/O I/O I/O I/O GND I/O (GLMX1) GL1 AGND NPECL1 AVDD PPECL1 (I/P) GL2 VDD I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD GND VDDP GND I/O I/O Pin Number 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 APA075 Function I/O I/O I/O I/O TCK TDI TMS VDDP GND VPP VPN TDO TRST RCK I/O I/O I/O GL3 PPECL2 (I/P) AVDD NPECL2 AGND GL4 I/O (GLMX2) GND VDD I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O APA150 Function I/O I/O I/O I/O TCK TDI TMS VDDP GND VPP VPN TDO TRST RCK I/O I/O I/O GL3 PPECL2 (I/P) AVDD NPECL2 AGND GL4 I/O (GLMX2) GND VDD I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O v3.0 63 Pr o A S I C P L U S F la s h F a m il y F P GA s 100- P in T Q FP Pin Number 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 APA075 Function I/O GND VDDP GND VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP APA150 Function I/O GND VDDP GND VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP 64 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s Pa c ka ge P i n A s si g nm e n t s 144-Pin TQFP 144 1 144-Pin TQFP v3.0 65 Pr o A S I C P L U S F la s h F a m il y F P GA s 144- P in T Q FP 1 44- Pi n T Q F P 14 4-P i n T Q FP 144- P in T Q FP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 APA075 Function I/O I/O I/O I/O I/O I/O I/O I/O VDD GND VDDP I/O I/O I/O GL GL AGND NPECL AVDD PPECL (I/P) I/O (GLMX) I/O I/O I/O I/O I/O GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Number 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 APA075 Function I/O I/O VDD GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD GND VDDP I/O I/O I/O I/O TCK TDI TMS NC VPP VPN TDO TRST RCK I/O I/O I/O VDDP GND I/O I/O Pin Number 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 APA075 Function I/O I/O I/O I/O (GLMX) PPECL (I/P) AVDD NPECL AGND GL GL I/O I/O I/O VDDP GND VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD I/O I/O I/O I/O I/O I/O I/O Pin Number 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 APA075 Function I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD I/O I/O I/O I/O I/O I/O I/O I/O 66 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s Pa c ka ge P i n A s si g nm e n t s (Continued) 208- P in P Q FP 1 208 208-Pin PQFP v3.0 67 Pr o A S I C P L U S F la s h F a m il y F P GA s 208- P in P Q FP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 APA075 Function GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD GND I/O I/O I/O I/O VDDP I/O (GLMX1) GL1 AGND NPECL1 AVDD GND GL2 I/O I/O I/O I/O I/O VDD I/O I/O I/O VDDP GND I/O APA150 Function GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD GND I/O I/O I/O I/O VDDP I/O (GLMX1) GL1 AGND NPECL1 AVDD GND GL2 I/O I/O I/O I/O I/O VDD I/O I/O I/O VDDP GND I/O APA300 Function GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD GND I/O I/O I/O I/O VDDP I/O (GLMX1) GL1 AGND NPECL1 AVDD GND GL2 I/O I/O I/O I/O I/O VDD I/O I/O I/O VDDP GND I/O APA450 Function GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD GND I/O I/O I/O I/O VDDP I/O (GLMX1) GL1 AGND NPECL1 AVDD GND GL2 I/O I/O I/O I/O I/O VDD I/O I/O I/O VDDP GND I/O APA600 Function GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD GND I/O I/O I/O I/O VDDP I/O (GLMX1) GL1 AGND NPECL1 AVDD GND GL2 I/O I/O I/O I/O I/O VDD I/O I/O I/O VDDP GND I/O APA750 Function GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD GND I/O I/O I/O I/O VDDP I/O (GLMX1) GL1 AGND NPECL1 AVDD GND GL2 I/O I/O I/O I/O I/O VDD I/O I/O I/O VDDP GND I/O APA1000 Function GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD GND I/O I/O I/O I/O VDDP I/O (GLMX1) GL1 AGND NPECL1 AVDD GND GL2 I/O I/O I/O I/O I/O VDD I/O I/O I/O VDDP GND I/O PPECL1 (I/P) PPECL1 (I/P) PPECL1 (I/P) PPECL1 (I/P) PPECL1 (I/P) PPECL1 (I/P) PPECL1 (I/P) 68 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 208- P in P Q FP (C ont inu ed) Pin Number 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 APA075 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O APA150 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O APA300 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O APA450 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O APA600 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O APA750 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O v3.0 69 Pr o A S I C P L U S F la s h F a m il y F P GA s 208- P in P Q FP (C ont inu ed) Pin Number 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 APA075 Function I/O I/O I/O VDD VDDP I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O TCK TDI TMS VDDP GND VPP VPN TDO TRST RCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O VDD APA150 Function I/O I/O I/O VDD VDDP I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O TCK TDI TMS VDDP GND VPP VPN TDO TRST RCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O VDD APA300 Function I/O I/O I/O VDD VDDP I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O TCK TDI TMS VDDP GND VPP VPN TDO TRST RCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O VDD APA450 Function I/O I/O I/O VDD VDDP I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O TCK TDI TMS VDDP GND VPP VPN TDO TRST RCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O VDD APA600 Function I/O I/O I/O VDD VDDP I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O TCK TDI TMS VDDP GND VPP VPN TDO TRST RCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O VDD APA750 Function I/O I/O I/O VDD VDDP I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O TCK TDI TMS VDDP GND VPP VPN TDO TRST RCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O VDD APA1000 Function I/O I/O I/O VDD VDDP I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O TCK TDI TMS VDDP GND VPP VPN TDO TRST RCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O VDD 70 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 208- P in P Q FP (C ont inu ed) Pin Number 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 APA075 Function I/O GL3 GND AVDD NPECL2 AGND GL4 I/O (GLMX2) I/O I/O VDDP I/O I/O GND VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O APA150 Function I/O GL3 GND AVDD NPECL2 AGND GL4 I/O (GLMX2) I/O I/O VDDP I/O I/O GND VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O APA300 Function I/O GL3 GND AVDD NPECL2 AGND GL4 I/O (GLMX2) I/O I/O VDDP I/O I/O GND VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O APA450 Function I/O GL3 GND AVDD NPECL2 AGND GL4 I/O (GLMX2) I/O I/O VDDP I/O I/O GND VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O APA600 Function I/O GL3 GND AVDD NPECL2 AGND GL4 I/O (GLMX2) I/O I/O VDDP I/O I/O GND VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O APA750 Function I/O GL3 GND AVDD NPECL2 AGND GL4 I/O (GLMX2) I/O I/O VDDP I/O I/O GND VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O APA1000 Function I/O GL3 GND AVDD NPECL2 AGND GL4 I/O (GLMX2) I/O I/O VDDP I/O I/O GND VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O PPECL2 (I/P) PPECL2 (I/P) PPECL2 (I/P) PPECL2 (I/P) PPECL2 (I/P) PPECL2 (I/P) PPECL2 (I/P) v3.0 71 Pr o A S I C P L U S F la s h F a m il y F P GA s 208- P in P Q FP (C ont inu ed) Pin Number 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 APA075 Function I/O VDDP VDD I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VDDP VDD I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP APA150 Function I/O VDDP VDD I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VDDP VDD I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP APA300 Function I/O VDDP VDD I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VDDP VDD I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP APA450 Function I/O VDDP VDD I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VDDP VDD I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP APA600 Function I/O VDDP VDD I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VDDP VDD I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP APA750 Function I/O VDDP VDD I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VDDP VDD I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP APA1000 Function I/O VDDP VDD I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VDDP VDD I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP 72 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s Pa c ka ge P i n A s si g nm e n t s (Continued) 456- P in P BGA (B ott om Vi ew) A1 Ball Pad Corner 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF v3.0 73 Pr o A S I C P L U S F la s h F a m il y F P GA s 4 5 6 - P in P BG A Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function VDDP VDDP NC NC NC NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC NC NC NC NC VDDP VDDP VDDP VDDP NC NC NC NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP NC NC NC NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC NC NC NC NC VDDP VDDP VDDP VDDP NC NC NC NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP VDDP VDDP NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 74 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 456- P in P BGA (C ont inu ed) Pin Number B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 D1 D2 D3 D4 D5 D6 APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function I/O I/O I/O NC NC NC NC NC VDDP VDDP VDDP NC VDDP NC NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC NC NC VDDP NC NC NC NC NC VDDP NC NC I/O I/O I/O NC NC NC NC NC VDDP VDDP VDDP I/O VDDP NC NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC NC NC VDDP NC NC NC NC I/O VDDP NC NC I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP VDDP I/O VDDP NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP NC NC NC NC I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP VDDP I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP I/O I/O I/O I/O I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP VDDP I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP I/O I/O I/O I/O I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP VDDP I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP I/O I/O I/O I/O I/O VDDP I/O I/O v3.0 75 Pr o A S I C P L U S F la s h F a m il y F P GA s 456- P in P BGA (C ont inu ed) Pin Number D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC VDDP NC NC NC NC NC NC NC VDD VDD VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC VDDP I/O NC NC I/O I/O I/O I/O VDD VDD VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP I/O NC NC I/O I/O I/O I/O VDD VDD VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP I/O I/O I/O I/O I/O I/O I/O VDD VDD VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP I/O I/O I/O I/O I/O I/O I/O VDD VDD VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP I/O I/O I/O I/O I/O I/O I/O VDD VDD VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD VDD 76 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 456- P in P BGA (C ont inu ed) Pin Number E23 E24 E25 E26 F1 F2 F3 F4 F5 F22 F23 F24 F25 F26 G1 G2 G3 G4 G5 G22 G23 G24 G25 G26 H1 H2 H3 H4 H5 H22 H23 H24 H25 H26 J1 J2 J3 J4 J5 J22 J23 J24 APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function NC NC NC NC NC NC NC NC VDD VDD NC NC NC NC I/O I/O NC NC VDD VDD NC NC NC I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O v3.0 77 Pr o A S I C P L U S F la s h F a m il y F P GA s 456- P in P BGA (C ont inu ed) Pin Number J25 J26 K1 K2 K3 K4 K5 K22 K23 K24 K25 K26 L1 L2 L3 L4 L5 L11 L12 L13 L14 L15 L16 L22 L23 L24 L25 L26 M1 M2 M3 M4 M5 M11 M12 M13 M14 M15 M16 M22 M23 M24 APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O I/O I/O I/O I/O GL1 GL2 I/O I/O I/O GND GND GND GND GND GND GL4 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O I/O I/O I/O I/O GL1 GL2 I/O I/O I/O GND GND GND GND GND GND GL4 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O I/O I/O I/O I/O GL1 GL2 I/O I/O I/O GND GND GND GND GND GND GL4 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O I/O I/O I/O I/O GL1 GL2 I/O I/O I/O GND GND GND GND GND GND GL4 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O I/O I/O I/O I/O GL1 GL2 I/O I/O I/O GND GND GND GND GND GND GL4 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O I/O I/O I/O I/O GL1 GL2 I/O I/O I/O GND GND GND GND GND GND GL4 I/O I/O 78 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 456- P in P BGA (C ont inu ed) Pin Number M25 M26 N1 N2 N3 N4 N5 N11 N12 N13 N14 N15 N16 N22 N23 N24 N25 N26 P1 P2 P3 P4 P5 P11 P12 P13 P14 P15 P16 P22 P23 P24 P25 P26 R1 R2 R3 R4 R5 R11 R12 R13 APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function I/O I/O I/O I/O (GLMX1) AGND PPECL1 (I/P) AVDD GND GND GND GND GND GND NPECL2 GL3 AVDD I/O (GLMX2) AGND I/O I/O I/O I/O NPECL1 GND GND GND GND GND GND I/O I/O I/O I/O PPECL2 (I/P) I/O I/O I/O I/O I/O GND GND GND I/O I/O I/O I/O (GLMX)1 AGND PPECL1 (I/P) AVDD GND GND GND GND GND GND NPECL2 GL3 AVDD I/O (GLMX) AGND I/O I/O I/O I/O NPECL1 GND GND GND GND GND GND I/O I/O I/O I/O PPECL2 (I/P) I/O I/O I/O I/O I/O GND GND GND I/O I/O I/O I/O (GLMX1) AGND PPECL1 (I/P) AVDD GND GND GND GND GND GND NPECL2 GL3 AVDD I/O (GLMX2) AGND I/O I/O I/O I/O NPECL1 GND GND GND GND GND GND I/O I/O I/O I/O PPECL2 (I/P) I/O I/O I/O I/O I/O GND GND GND I/O I/O I/O I/O (GLMX1) AGND PPECL1 (I/P) AVDD GND GND GND GND GND GND NPECL2 GL3 AVDD I/O (GLMX2) AGND I/O I/O I/O I/O NPECL1 GND GND GND GND GND GND I/O I/O I/O I/O PPECL2 (I/P) I/O I/O I/O I/O I/O GND GND GND I/O I/O I/O I/O (GLMX1) AGND PPECL1 (I/P) AVDD GND GND GND GND GND GND NPECL2 GL3 AVDD I/O (GLMX2) AGND I/O I/O I/O I/O NPECL1 GND GND GND GND GND GND I/O I/O I/O I/O PPECL2 (I/P) I/O I/O I/O I/O I/O GND GND GND I/O I/O I/O I/O (GLMX1) AGND PPECL1 (I/P) AVDD GND GND GND GND GND GND NPECL2 GL3 AVDD I/O (GLMX2) AGND I/O I/O I/O I/O NPECL1 GND GND GND GND GND GND I/O I/O I/O I/O PPECL2 (I/P) I/O I/O I/O I/O I/O GND GND GND v3.0 79 Pr o A S I C P L U S F la s h F a m il y F P GA s 456- P in P BGA (C ont inu ed) Pin Number R14 R15 R16 R22 R23 R24 R25 R26 T1 T2 T3 T4 T5 T11 T12 T13 T14 T15 T16 T22 T23 T24 T25 T26 U1 U2 U3 U4 U5 U22 U23 U24 U25 U26 V1 V2 V3 V4 V5 V22 V23 V24 APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 80 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 456- P in P BGA (C ont inu ed) Pin Number V25 V26 W1 W2 W3 W4 W5 W22 W23 W24 W25 W26 Y1 Y2 Y3 Y4 Y5 Y22 Y23 Y24 Y25 Y26 AA1 AA2 AA3 AA4 AA5 AA22 AA23 AA24 AA25 AA26 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O NC VDD VDD NC NC NC NC I/O NC NC NC VDD VDD NC NC NC NC NC NC NC NC VDD VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD VDD I/O I/O I/O v3.0 81 Pr o A S I C P L U S F la s h F a m il y F P GA s 456- P in P BGA (C ont inu ed) Pin Number AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD VDD NC NC NC NC NC NC NC VDDP NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS TDO VDDP RCK NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD VDD I/O I/O I/O NC I/O I/O I/O VDDP NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS TDO VDDP RCK NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD VDD I/O I/O I/O NC I/O I/O I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS TDO VDDP RCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD VDD I/O I/O I/O I/O I/O I/O I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS TDO VDDP RCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD VDD I/O I/O I/O I/O I/O I/O I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS TDO VDDP RCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD VDD I/O I/O I/O I/O I/O I/O I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS TDO VDDP RCK I/O I/O 82 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 456- P in P BGA (C ont inu ed) Pin Number AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function NC NC VDDP NC NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC TCK VPP NC VDDP NC NC VDDP VDDP NC NC NC NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I/O VDDP NC NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC TCK VPP NC VDDP NC NC VDDP VDDP NC NC NC NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK VPP NC VDDP I/O I/O VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK VPP I/O VDDP I/O I/O VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK VPP I/O VDDP I/O I/O VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK VPP I/O VDDP I/O I/O VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O v3.0 83 Pr o A S I C P L U S F la s h F a m il y F P GA s 456- P in P BGA (C ont inu ed) Pin Number AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function I/O I/O I/O NC NC NC VPN TRST VDDP VDDP VDDP VDDP NC NC NC NC NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O NC NC NC NC NC TDI NC VDDP VDDP I/O I/O I/O NC NC NC VPN TRST VDDP VDDP VDDP VDDP NC NC NC NC NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O NC NC NC NC NC TDI NC VDDP VDDP I/O I/O I/O I/O I/O I/O VPN TRST VDDP VDDP VDDP VDDP I/O I/O I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDI I/O VDDP VDDP I/O I/O I/O I/O I/O I/O VPN TRST VDDP VDDP VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDI I/O VDDP VDDP I/O I/O I/O I/O I/O I/O VPN TRST VDDP VDDP VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDI I/O VDDP VDDP I/O I/O I/O I/O I/O I/O VPN TRST VDDP VDDP VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDI I/O VDDP VDDP 84 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s Pa c ka ge A ss i gn m e nt s (Continued) 144- FB GA (Bot t om V iew ) A1 Ball Pad Corner 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M v3.0 85 Pr o A S I C P L U S F la s h F a m il y F P GA s 144- FB GA P i n 14 4-FB GA P in (Co nti nue d) Pin APA075 Number Function A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 D1 D2 D3 D4 D5 D6 I/O I/O I/O I/O I/O GND I/O VDD I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O GL2 I/O VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA150 Function I/O I/O I/O I/O I/O GND I/O VDD I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O GL2 I/O VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA300 Function I/O I/O I/O I/O I/O GND I/O VDD I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O GL2 I/O VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA450 Function I/O I/O I/O I/O I/O GND I/O VDD I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O GL2 I/O VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin APA075 Number Function D7 D8 D9 D10 D11 D12 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 G1 G2 G3 G4 G5 G6 G7 G8 G9 I/O I/O I/O I/O I/O I/O (GLMX2) VDD I/O I/O VDDP I/O VDDP VDDP AVDD VDDP VDD NPECL2 AGND GL1 AGND I/O (GLMX1) I/O GND GND GND I/O GL4 GND PPECL2 (I/P) GL3 PPECL1 (I/P) GND AVDD NPECL1 GND GND GND I/O I/O APA150 Function I/O I/O I/O I/O I/O I/O (GLMX2) VDD I/O I/O VDDP I/O VDDP VDDP AVDD VDDP VDD NPECL2 AGND GL1 AGND I/O (GLMX1) I/O GND GND GND I/O GL4 GND PPECL2 (I/P) GL3 PPECL1 (I/P) GND AVDD NPECL1 GND GND GND I/O I/O APA300 Function I/O I/O I/O I/O I/O I/O (GLMX2) VDD I/O I/O VDDP I/O VDDP VDDP AVDD VDDP VDD NPECL2 AGND GL1 AGND I/O (GLMX1) I/O GND GND GND I/O GL4 GND PPECL2 (I/P) GL3 PPECL1 (I/P) GND AVDD NPECL1 GND GND GND I/O I/O APA450 Function I/O I/O I/O I/O I/O I/O (GLMX2) VDD I/O I/O VDDP I/O VDDP VDDP AVDD VDDP VDD NPECL2 AGND GL1 AGND I/O (GLMX1) I/O GND GND GND I/O GL4 GND PPECL2 (I/P) GL3 PPECL1 (I/P) GND AVDD NPECL1 GND GND GND I/O I/O 86 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 144- FB GA Pi n ( Cont i nued) 144- FB GA Pi n ( Cont i nued) Pin APA075 Number Function G10 G11 G12 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 L1 L2 L3 I/O I/O I/O VDD I/O I/O I/O VDD I/O I/O I/O I/O VDDP I/O VDD I/O I/O VDDP I/O I/O I/O VDD TCK I/O TDO I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O GND I/O I/O GND I/O I/O APA150 Function I/O I/O I/O VDD I/O I/O I/O VDD I/O I/O I/O I/O VDDP I/O VDD I/O I/O VDDP I/O I/O I/O VDD TCK I/O TDO I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O GND I/O I/O GND I/O I/O APA300 Function I/O I/O I/O VDD I/O I/O I/O VDD I/O I/O I/O I/O VDDP I/O VDD I/O I/O VDDP I/O I/O I/O VDD TCK I/O TDO I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O GND I/O I/O GND I/O I/O APA450 Function I/O I/O I/O VDD I/O I/O I/O VDD I/O I/O I/O I/O VDDP I/O VDD I/O I/O VDDP I/O I/O I/O VDD TCK I/O TDO I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O GND I/O I/O GND I/O I/O Pin APA075 Number Function L4 L5 L6 L7 L8 L9 L10 L11 L12 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 I/O VDDP I/O I/O I/O TMS RCK I/O TRST I/O I/O I/O I/O I/O I/O I/O I/O TDI VDDP VPP VPN APA150 Function I/O VDDP I/O I/O I/O TMS RCK I/O TRST I/O I/O I/O I/O I/O I/O I/O I/O TDI VDDP VPP VPN APA300 Function I/O VDDP I/O I/O I/O TMS RCK I/O TRST I/O I/O I/O I/O I/O I/O I/O I/O TDI VDDP VPP VPN APA450 Function I/O VDDP I/O I/O I/O TMS RCK I/O TRST I/O I/O I/O I/O I/O I/O I/O I/O TDI VDDP VPP VPN v3.0 87 Pr o A S I C P L U S F la s h F a m il y F P GA s Pa c ka ge A ss i gn m e nt s (Continued) 256- FB GA ( Bot t om V iew ) A1 Ball Pad Corner 16 15 14 13 12 11 10 9 8 7654 321 A B C D E F G H J K L M N P R T 88 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 256- P in FBG A Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 APA150 Function GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA300 Function GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA450 Function GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA600 Function GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O v3.0 89 Pr o A S I C P L U S F la s h F a m il y F P GA s 256- P in FBG A ( Cont i nued) Pin Number C14 C15 C16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 APA150 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP I/O I/O VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD VDD VDD VDD APA300 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP I/O I/O VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD VDD VDD VDD APA450 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP I/O I/O VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD VDD VDD VDD APA600 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP I/O I/O VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD VDD VDD VDD 90 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 256- P in FBG A ( Cont i nued) Pin Number F11 F12 F13 F14 F15 F16 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 J1 J2 J3 J4 J5 J6 J7 APA150 Function GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD GND GND GND GND VDD VDDP I/O I/O I/O I/O GL1 NPECL1 I/O (GLMX1) AGND I/O VDD GND GND GND GND VDD I/O I/O (GLMX2) NPECL2 AGND GL4 GL2 PPECL1 (I/P) AVDD I/O I/O VDD GND APA300 Function GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD GND GND GND GND VDD VDDP I/O I/O I/O I/O GL1 NPECL1 I/O (GLMX1) AGND I/O VDD GND GND GND GND VDD I/O I/O (GLMX2) NPECL2 AGND GL4 GL2 PPECL1 (I/P) AVDD I/O I/O VDD GND APA450 Function GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD GND GND GND GND VDD VDDP I/O I/O I/O I/O GL1 NPECL1 I/O (GLMX1) AGND I/O VDD GND GND GND GND VDD I/O I/O (GLMX2) NPECL2 AGND GL4 GL2 PPECL1 (I/P) AVDD I/O I/O VDD GND APA600 Function GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD GND GND GND GND VDD VDDP I/O I/O I/O I/O GL1 NPECL1 I/O (GLMX1) AGND I/O VDD GND GND GND GND VDD I/O I/O (GLMX2) NPECL2 AGND GL4 GL2 PPECL1 (I/P) AVDD I/O I/O VDD GND v3.0 91 Pr o A S I C P L U S F la s h F a m il y F P GA s 256- P in FBG A ( Cont i nued) Pin Number J8 J9 J10 J11 J12 J13 J14 J15 J16 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 M1 M2 M3 M4 APA150 Function GND GND GND VDD I/O PPECL2 (I/P) I/O AVDD GL3 I/O I/O I/O I/O VDDP VDD GND GND GND GND VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD VDD VDD VDD GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O APA300 Function GND GND GND VDD I/O PPECL2 (I/P) I/O AVDD GL3 I/O I/O I/O I/O VDDP VDD GND GND GND GND VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD VDD VDD VDD GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O APA450 Function GND GND GND VDD I/O PPECL2 (I/P) I/O AVDD GL3 I/O I/O I/O I/O VDDP VDD GND GND GND GND VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD VDD VDD VDD GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O APA600 Function GND GND GND VDD I/O PPECL2 (I/P) I/O AVDD GL3 I/O I/O I/O I/O VDDP VDD GND GND GND GND VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD VDD VDD VDD GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O 92 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 256- P in FBG A ( Cont i nued) Pin Number M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 R1 APA150 Function I/O VDDP VDDP I/O I/O VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O RCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK VPP TRST I/O I/O APA300 Function I/O VDDP VDDP I/O I/O VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O RCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK VPP TRST I/O I/O APA450 Function I/O VDDP VDDP I/O I/O VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O RCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK VPP TRST I/O I/O APA600 Function I/O VDDP VDDP I/O I/O VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O RCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK VPP TRST I/O I/O v3.0 93 Pr o A S I C P L U S F la s h F a m il y F P GA s 256- P in FBG A ( Cont i nued) Pin Number R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 APA150 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDI VPN TDO GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS GND APA300 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDI VPN TDO GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS GND APA450 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDI VPN TDO GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS GND APA600 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDI VPN TDO GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS GND 94 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s Pa c ka ge A ss i gn m e nt s (Continued) 484-Pin FBGA (Bottom View) A1 Ball Pad Corner 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB v3.0 95 Pr o A S I C P L U S F la s h F a m il y F P GA s 484- P in FBG A 48 4-P i n FB GA (Co nti nue d) Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 APA450 Function GND GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND GND GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA600 Function GND GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND GND GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Number B21 B22 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 APA450 Function VDDP GND VDDP NC I/O I/O GND I/O I/O VDD VDD I/O I/O NC NC VDD VDD NC I/O GND I/O I/O I/O VDDP I/O I/O NC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA600 Function VDDP GND VDDP I/O I/O I/O GND I/O I/O VDD VDD I/O I/O I/O I/O VDD VDD I/O I/O GND I/O I/O I/O VDDP I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 96 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 484- P in FBG A ( Cont i nued) 484- P in FB GA ( Cont i nued) Pin Number D19 D20 D21 D22 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 APA450 Function GND I/O I/O I/O I/O NC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA600 Function GND I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Number F17 F18 F19 F20 F21 F22 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 APA450 Function I/O I/O I/O I/O I/O NC I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD I/O I/O I/O I/O I/O VDDP VDDP I/O I/O VDDP VDDP APA600 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD I/O I/O I/O I/O I/O VDDP VDDP I/O I/O VDDP VDDP v3.0 97 Pr o A S I C P L U S F la s h F a m il y F P GA s 484- P in FBG A ( Cont i nued) 48 4-P i n FB GA (Co nti nue d) Pin Number H15 H16 H17 H18 H19 H20 H21 H22 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 APA450 Function I/O I/O I/O I/O I/O VDD I/O I/O I/O I/O NC I/O I/O I/O I/O VDDP GND VDD VDD VDD VDD GND VDDP I/O I/O I/O I/O NC I/O I/O I/O I/O NC I/O I/O I/O I/O VDDP VDD GND GND GND APA600 Function I/O I/O I/O I/O I/O VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD VDD VDD VDD GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD GND GND GND Pin Number K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 APA450 Function GND VDD VDDP I/O I/O I/O I/O I/O I/O I/O NC I/O I/O GL1 NPECL1 I/O (GLMX1) AGND I/O VDD GND GND GND GND VDD I/O I/O (GLMX2) NPECL2 AGND GL4 I/O I/O I/O I/O I/O I/O GL2 PPECL1 (I/P) AVDD I/O I/O VDD GND APA600 Function GND VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GL1 NPECL1 I/O (GLMX1) AGND I/O VDD GND GND GND GND VDD I/O I/O (GLMX2) NPECL2 AGND GL4 I/O I/O I/O I/O I/O I/O GL2 PPECL1 (I/P) AVDD I/O I/O VDD GND 98 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 484- P in FBG A ( Cont i nued) 484- P in FB GA ( Cont i nued) Pin Number M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 P1 P2 P3 P4 P5 P6 P7 P8 APA450 Function GND GND GND VDD I/O PPECL2 (I/P) I/O AVDD GL3 I/O I/O I/O I/O I/O NC I/O I/O I/O I/O VDDP VDD GND GND GND GND VDD VDDP I/O I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP APA600 Function GND GND GND VDD I/O PPECL2 (I/P) I/O AVDD GL3 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD GND GND GND GND VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP Pin Number P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 T1 T2 T3 T4 T5 T6 APA450 Function GND VDD VDD VDD VDD GND VDDP I/O I/O I/O I/O NC I/O I/O I/O I/O VDD I/O I/O I/O I/O I/O VDDP VDDP I/O I/O VDDP VDDP I/O I/O I/O I/O I/O VDD I/O I/O I/O I/O NC I/O I/O I/O APA600 Function GND VDD VDD VDD VDD GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD I/O I/O I/O I/O I/O VDDP VDDP I/O I/O VDDP VDDP I/O I/O I/O I/O I/O VDD I/O I/O I/O I/O I/O I/O I/O I/O v3.0 99 Pr o A S I C P L U S F la s h F a m il y F P GA s 484- P in FBG A ( Cont i nued) 48 4-P i n FB GA (Co nti nue d) Pin Number T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 V1 V2 V3 V4 APA450 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O RCK I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK VPP TRST I/O NC I/O I/O I/O I/O GND I/O APA600 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O RCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK VPP TRST I/O I/O I/O I/O I/O I/O GND I/O Pin Number V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 Y1 Y2 APA450 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDI VPN TDO GND NC I/O NC I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS GND NC NC I/O VDDP I/O APA600 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDI VPN TDO GND I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS GND I/O I/O I/O VDDP I/O 100 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 484- P in FBG A ( Cont i nued) 484- P in FB GA ( Cont i nued) Pin Number Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 APA450 Function I/O I/O GND I/O I/O VDD VDD I/O I/O I/O I/O VDD VDD I/O I/O GND I/O I/O NC VDDP GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC NC I/O VDDP GND APA600 Function I/O I/O GND I/O I/O VDD VDD I/O I/O I/O I/O VDD VDD I/O I/O GND I/O I/O I/O VDDP GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND Pin Number AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 APA450 Function GND GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I/O VDDP GND GND APA600 Function GND GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND GND v3.0 101 Pr o A S I C P L U S F la s h F a m il y F P GA s Pa c ka ge P i n A s si g nm e n t s (Continued) 676- P in FBG A ( Bot t om V iew ) A1 Ball Pad Corner 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 102 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 676- FB GA Pi n 676- FB GA Pi n ( Cont i nued) Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 APA600 Function GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA750 Function GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Number B18 B19 B20 B21 B22 B23 B24 B25 B26 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 D1 D2 D3 D4 D5 D6 D7 D8 APA600 Function I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O APA750 Function I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O v3.0 103 Pr o A S I C P L U S F la s h F a m il y F P GA s 676- FB GA P i n ( Cont i nued) 67 6-FB GA P in (Co nti nue d) Pin Number D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 APA600 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA750 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Number E26 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 APA600 Function I/O I/O I/O I/O I/O GND I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD NC I/O NC I/O NC I/O NC I/O APA750 Function I/O I/O I/O I/O I/O GND I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD NC I/O NC I/O NC I/O NC I/O 104 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 676- FB GA Pi n ( Cont i nued) 676- FB GA Pi n ( Cont i nued) Pin Number G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 J1 J2 J3 J4 J5 J6 J7 APA600 Function NC I/O VDDP NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC APA750 Function NC I/O VDDP NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC Pin Number J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 APA600 Function VDDP VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDP NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP I/O I/O I/O I/O I/O APA750 Function VDDP VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDP NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP I/O I/O I/O I/O I/O v3.0 105 Pr o A S I C P L U S F la s h F a m il y F P GA s 676- FB GA P i n ( Cont i nued) 67 6-FB GA P in (Co nti nue d) Pin Number K25 K26 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 L24 L25 L26 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 APA600 Function I/O I/O I/O I/O I/O I/O I/O I/O NC VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD GND GND GND GND GND GND APA750 Function I/O I/O I/O I/O I/O I/O I/O I/O NC VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD GND GND GND GND GND GND Pin Number M16 M17 M18 M19 M20 M21 M22 M23 M24 M25 M26 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 N23 N24 N25 N26 P1 P2 P3 P4 P5 P6 APA600 Function GND GND VDD VDDP I/O I/O I/O I/O I/O I/O I/O GL1 AGND I/O (GLMX1) I/O NPECL1 I/O NC VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP NC I/O GL3 I/O NPECL2 GL4 I/O GL2 AVDD I/O I/O PPECL1 (I/P) I/O APA750 Function GND GND VDD VDDP I/O I/O I/O I/O I/O I/O I/O GL1 AGND I/O (GLMX1) I/O NPECL1 I/O NC VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP NC I/O GL3 I/O NPECL2 GL4 I/O GL2 AVDD I/O I/O PPECL1 (I/P) I/O 106 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 676- FB GA Pi n ( Cont i nued) 676- FB GA Pi n ( Cont i nued) Pin Number P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 APA600 Function I/O VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP I/O I/O I/O (GLMX2) I/O PPECL2 (I/P) AVDD AGND I/O I/O I/O I/O I/O I/O NC VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP NC I/O I/O I/O APA750 Function I/O VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP I/O I/O I/O (GLMX2) I/O PPECL2 (I/P) AVDD AGND I/O I/O I/O I/O I/O I/O NC VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP NC I/O I/O I/O Pin Number R24 R25 R26 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 APA600 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC VDDP VDD GND GND GND GND GND APA750 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC VDDP VDD GND GND GND GND GND v3.0 107 Pr o A S I C P L U S F la s h F a m il y F P GA s 676- FB GA P i n ( Cont i nued) 67 6-FB GA P in (Co nti nue d) Pin Number U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25 U26 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 W1 W2 W3 W4 W5 APA600 Function GND GND GND VDD VDDP NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA750 Function GND GND GND VDD VDDP NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Number W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 W26 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 APA600 Function I/O VDD VDD VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP NC I/O NC I/O NC I/O NC I/O NC I/O VDD VPP I/O I/O APA750 Function I/O VDD VDD VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP NC I/O NC I/O NC I/O NC I/O NC I/O VDD VPP I/O I/O 108 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 676- FB GA Pi n ( Cont i nued) 676- FB GA Pi n ( Cont i nued) Pin Number Y23 Y24 Y25 Y26 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 APA600 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDO GND GND I/O I/O I/O I/O I/O I/O I/O I/O GND GND I/O I/O I/O I/O I/O I/O APA750 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDO GND GND I/O I/O I/O I/O I/O I/O I/O I/O GND GND I/O I/O I/O I/O I/O I/O Pin Number AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD1 AD2 AD3 AD4 APA600 Function I/O I/O I/O I/O I/O I/O I/O TCK TRST I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS RCK I/O I/O I/O I/O I/O I/O I/O APA750 Function I/O I/O I/O I/O I/O I/O I/O TCK TRST I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS RCK I/O I/O I/O I/O I/O I/O I/O v3.0 109 Pr o A S I C P L U S F la s h F a m il y F P GA s 676- FB GA P i n ( Cont i nued) 67 6-FB GA P in (Co nti nue d) Pin Number AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 APA600 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDI VPN I/O I/O GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA750 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDI VPN I/O I/O GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Number AE22 AE23 AE24 AE25 AE26 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 APA600 Function I/O I/O I/O GND GND GND GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND APA750 Function I/O I/O I/O GND GND GND GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND 110 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s Pa c ka ge P i n A s si g nm e n t s (Continued) 896- P in FBG A ( Bot t om V iew ) A1 Ball Pad Corner 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK v3.0 111 Pr o A S I C P L U S F la s h F a m il y F P GA s 896 FB GA P i n 89 6 FB GA P in (Co nti nue d) Pin Number A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 APA750 Function GND GND I/O GND I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O GND I/O GND GND GND GND I/O VDD I/O VDD I/O I/O I/O I/O I/O I/O I/O I/O APA1000 Function GND GND I/O GND I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O GND I/O GND GND GND GND I/O VDD I/O VDD I/O I/O I/O I/O I/O I/O I/O I/O Pin Number B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 APA750 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD I/O VDD I/O GND GND GND I/O VDD I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD I/O VDD I/O GND GND GND I/O VDD I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP 112 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 896 FB GA Pi n ( Cont i nued) 896 FB GA Pi n ( Cont i nued) Pin Number C27 C28 C29 C30 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 E1 E2 E3 E4 E5 E6 E7 E8 APA750 Function I/O VDD NC GND I/O VDD I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O VDD I/O GND I/O VDDP I/O VDD I/O VDDP I/O APA1000 Function I/O VDD I/O GND I/O VDD I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O VDD I/O GND I/O VDDP I/O VDD I/O VDDP I/O Pin Number E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 APA750 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP I/O VDD I/O VDDP I/O GND I/O VDD I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP I/O VDD I/O VDDP I/O GND I/O VDD I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O v3.0 113 Pr o A S I C P L U S F la s h F a m il y F P GA s 896 FB GA P i n ( Cont i nued) 89 6 FB GA P in (Co nti nue d) Pin Number F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 H1 H2 APA750 Function I/O I/O I/O I/O GND I/O I/O I/O VDD I/O GND I/O I/O I/O VDDP I/O VDD I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP I/O VDD I/O VDDP I/O I/O I/O GND I/O I/O APA1000 Function I/O I/O I/O I/O GND I/O I/O I/O VDD I/O GND I/O I/O I/O VDDP I/O VDD I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP I/O VDD I/O VDDP I/O I/O I/O GND I/O I/O Pin Number H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 APA750 Function I/O I/O I/O I/O I/O GND NC NC NC NC NC NC NC NC NC NC NC NC NC NC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP I/O VDD NC NC NC NC NC APA1000 Function I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP I/O VDD I/O I/O I/O I/O I/O 114 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 896 FB GA Pi n ( Cont i nued) 896 FB GA Pi n ( Cont i nued) Pin Number J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 APA750 Function NC NC NC NC NC NC NC VDD I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC VDD NC VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP NC VDD NC I/O I/O I/O I/O APA1000 Function I/O I/O I/O I/O I/O I/O I/O VDD I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD I/O VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP I/O VDD I/O I/O I/O I/O I/O Pin Number K27 K28 K29 K30 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 L24 L25 L26 L27 L28 L29 L30 M1 M2 M3 M4 M5 M6 M7 M8 APA750 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC NC VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O v3.0 115 Pr o A S I C P L U S F la s h F a m il y F P GA s 896 FB GA P i n ( Cont i nued) 89 6 FB GA P in (Co nti nue d) Pin Number M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 M23 M24 M25 M26 M27 M28 M29 M30 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 APA750 Function NC VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC VDDP VDD GND GND GND GND GND GND GND GND VDD APA1000 Function I/O VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD GND GND GND GND GND GND GND GND VDD Pin Number N21 N22 N23 N24 N25 N26 N27 N28 N29 N30 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 R1 R2 APA750 Function VDDP NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (GLMX1) APA1000 Function VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (GLMX1) 116 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 896 FB GA Pi n ( Cont i nued) 896 FB GA Pi n ( Cont i nued) Pin Number R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 APA750 Function AGND NPECL1 GL1 I/O I/O I/O NC VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP I/O I/O I/O I/O I/O NPECL2 AGND I/O (GLMX2) I/O I/O AVDD GL2 PPECL1 (I/P) I/O I/O I/O I/O I/O VDDP VDD GND GND GND APA1000 Function AGND NPECL1 GL1 I/O I/O I/O I/O VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP I/O I/O I/O I/O I/O NPECL2 AGND I/O (GLMX2) I/O I/O AVDD GL2 PPECL1 (I/P) I/O I/O I/O I/O I/O VDDP VDD GND GND GND Pin Number T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25 U26 APA750 Function GND GND GND GND GND VDD VDDP I/O I/O I/O I/O PPECL2 (I/P) GL4 GL3 AVDD I/O I/O I/O I/O I/O I/O I/O I/O I/O NC VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP NC I/O I/O I/O I/O APA1000 Function GND GND GND GND GND VDD VDDP I/O I/O I/O I/O PPECL2 (I/P) GL4 GL3 AVDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP I/O I/O I/O I/O I/O v3.0 117 Pr o A S I C P L U S F la s h F a m il y F P GA s 896 FB GA P i n ( Cont i nued) 89 6 FB GA P in (Co nti nue d) Pin Number U27 U28 U29 U30 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29 V30 W1 W2 W3 W4 W5 W6 W7 W8 APA750 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Number W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 W26 W27 W28 W29 W30 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 APA750 Function NC VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC NC VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD APA1000 Function I/O VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD 118 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 896 FB GA Pi n ( Cont i nued) 896 FB GA Pi n ( Cont i nued) Pin Number Y21 Y22 Y23 Y24 Y25 Y26 Y27 Y28 Y29 Y30 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AA27 AA28 AA29 AA30 AB1 AB2 APA750 Function NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC VDD NC VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP NC VDD NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD I/O VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP I/O VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Number AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AB27 AB28 AB29 AB30 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 APA750 Function I/O I/O I/O I/O VDDP I/O VDD NC NC NC NC NC NC NC NC NC NC NC NC VDD I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND NC NC NC NC NC NC APA1000 Function I/O I/O I/O I/O VDDP I/O VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O v3.0 119 Pr o A S I C P L U S F la s h F a m il y F P GA s 896 FB GA P i n ( Cont i nued) 89 6 FB GA P in (Co nti nue d) Pin Number AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AC27 AC28 AC29 AC30 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 APA750 Function NC NC NC NC NC NC NC NC GND I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O VDDP I/O VDD I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP TCK VDD TRST VDDP APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O VDDP I/O VDD I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP TCK VDD TRST VDDP Pin Number AD27 AD28 AD29 AD30 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AE27 AE28 AE29 AE30 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 APA750 Function I/O I/O I/O GND I/O VDD I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O VDD I/O GND I/O VDDP I/O VDD I/O VDDP I/O APA1000 Function I/O I/O I/O GND I/O VDD I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O VDD I/O GND I/O VDDP I/O VDD I/O VDDP I/O 120 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 896 FB GA Pi n ( Cont i nued) 896 FB GA Pi n ( Cont i nued) Pin Number AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF27 AF28 AF29 AF30 AG1 AG2 AG3 AG4 AG5 AG6 AG7 AG8 AG9 AG10 AG11 AG12 AG13 AG14 AG15 AG16 AG17 AG18 AG19 AG20 APA750 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP I/O VDD TDO VDDP VPN GND I/O VDD I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP I/O VDD TDO VDDP VPN GND I/O VDD I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Number AG21 AG22 AG23 AG24 AG25 AG26 AG27 AG28 AG29 AG30 AH1 AH2 AH3 AH4 AH5 AH6 AH7 AH8 AH9 AH10 AH11 AH12 AH13 AH14 AH15 AH16 AH17 AH18 AH19 AH20 AH21 AH22 AH23 AH24 AH25 AH26 AH27 AH28 AH29 AH30 AJ1 AJ2 APA750 Function I/O I/O I/O I/O I/O I/O GND RCK VDD I/O GND I/O VDD I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP TDI VDD VPP GND GND GND APA1000 Function I/O I/O I/O I/O I/O I/O GND RCK VDD I/O GND I/O VDD I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP TDI VDD VPP GND GND GND v3.0 121 Pr o A S I C P L U S F la s h F a m il y F P GA s 896 FB GA P i n ( Cont i nued) 89 6 FB GA P in (Co nti nue d) Pin Number AJ3 AJ4 AJ5 AJ6 AJ7 AJ8 AJ9 AJ10 AJ11 AJ12 AJ13 AJ14 AJ15 AJ16 AJ17 AJ18 AJ19 AJ20 AJ21 AJ22 AJ23 AJ24 AJ25 AJ26 AJ27 AJ28 AJ29 AJ30 AK2 AK3 AK4 AK5 AK6 AK7 AK8 AK9 AK10 AK11 AK12 AK13 AK14 AK15 APA750 Function I/O VDD I/O VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD I/O VDD TMS GND GND GND GND I/O GND I/O GND I/O I/O I/O I/O I/O I/O I/O I/O APA1000 Function I/O VDD I/O VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD I/O VDD TMS GND GND GND GND I/O GND I/O GND I/O I/O I/O I/O I/O I/O I/O I/O Pin Number AK16 AK17 AK18 AK19 AK20 AK21 AK22 AK23 AK24 AK25 AK26 AK27 AK28 AK29 APA750 Function I/O I/O I/O I/O I/O I/O I/O I/O GND I/O GND I/O GND GND APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O GND I/O GND I/O GND GND 122 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s Pa c ka ge P i n A s si g nm e n t s (Continued) 1152-Pin FBGA (Bottom View) A1 Ball Pad Corner 34 33 32 31 30 2928 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AO AP v3.0 123 Pr o A S I C P L U S F la s h F a m il y F P GA s 1152 FB GA P in 1 152 FBG A P i n 1 1 5 2 F BG A P in 1152 FB GA P in Pin Number A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 APA1000 Function NC GND GND GND I/O VDD VDD VDD VDD I/O GND I/O VDDP VDDP I/O GND GND I/O VDDP VDDP I/O GND I/O VDD VDD VDD VDD I/O GND GND GND NC NC NC GND GND GND NC I/O NC I/O NC I/O GND I/O Pin Number B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 APA1000 Function VDDP VDDP I/O GND GND I/O VDDP VDDP I/O GND I/O NC I/O NC I/O NC GND GND GND NC NC GND GND NC GND GND I/O GND I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Number C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 E1 APA1000 Function I/O GND I/O GND I/O GND GND NC GND GND GND GND GND GND I/O VDD I/O VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD I/O VDD I/O GND GND GND GND GND Pin Number E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 E31 E32 E33 E34 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 APA1000 Function GND GND I/O VDD I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP I/O VDD I/O GND GND GND I/O NC I/O VDD I/O GND I/O I/O I/O I/O I/O I/O 124 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 1152 FB GA P in 1152 FB GA P in 1152 FB GA P in 115 2 FB GA P in Pin Number F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O VDD I/O NC NC VDD I/O GND I/O VDDP I/O VDD I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Number G24 G25 G26 G27 G28 G29 G30 G31 G32 G33 G34 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30 H31 H32 H33 H34 APA1000 Function I/O I/O VDDP I/O VDD I/O VDDP I/O GND I/O VDD VDD NC I/O VDD I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O VDD I/O NC VDD Pin Number J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 J31 J32 J33 J34 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 APA1000 Function VDD I/O GND I/O I/O I/O VDDP I/O VDD I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP I/O VDD I/O VDDP I/O I/O I/O GND I/O VDD VDD NC I/O I/O I/O I/O I/O I/O I/O GND I/O Pin Number K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K30 K31 K32 K33 K34 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O NC VDD I/O I/O I/O I/O I/O I/O I/O I/O VDDP I/O VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O v3.0 125 Pr o A S I C P L U S F la s h F a m il y F P GA s 1152 FB GA P in 1 152 FBG A P i n 1 1 5 2 F BG A P in 1152 FB GA P in Pin Number L23 L24 L25 L26 L27 L28 L29 L30 L31 L32 L33 L34 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 M23 M24 M25 M26 M27 M28 M29 M30 M31 M32 M33 APA1000 Function I/O VDD I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD I/O VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP I/O VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O GND Pin Number M34 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 N23 N24 N25 N26 N27 N28 N29 N30 N31 N32 N33 N34 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 APA1000 Function GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O Pin Number P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 APA1000 Function I/O VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD GND GND GND GND GND GND GND GND Pin Number R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 R32 R33 R34 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 APA1000 Function VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O 126 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 1152 FB GA P in 1152 FB GA P in 1152 FB GA P in 115 2 FB GA P in Pin Number T33 T34 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25 U26 U27 U28 U29 U30 U31 U32 U33 U34 V1 V2 V3 V4 V5 V6 APA1000 Function I/O I/O GND GND I/O I/O (GLMX1) AGND NPECL1 GL1 I/O I/O I/O I/O VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP I/O I/O I/O I/O I/O NPECL2 AGND I/O (GLMX2) I/O GND GND GND GND I/O AVDD GL2 PPECL1 (I/P) Pin Number V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29 V30 V31 V32 V33 V34 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 APA1000 Function I/O I/O I/O I/O I/O VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP I/O I/O I/O I/O PPECL2 (I/P) GL4 GL3 AVDD I/O GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD GND GND GND Pin Number W17 W18 W19 W20 W21 W22 W23 W24 W25 W26 W27 W28 W29 W30 W31 W32 W33 W34 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Y25 Y26 Y27 APA1000 Function GND GND GND GND GND VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP I/O I/O I/O I/O Pin Number Y28 Y29 Y30 Y31 Y32 Y33 Y34 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AA27 AA28 AA29 AA30 AA31 AA32 AA33 AA34 AB1 AB2 AB3 AB4 APA1000 Function I/O I/O I/O I/O I/O VDDP VDDP VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP I/O I/O I/O I/O v3.0 127 Pr o A S I C P L U S F la s h F a m il y F P GA s 1152 FB GA P in 1 152 FBG A P i n 1 1 5 2 F BG A P in 1152 FB GA P in Pin Number AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AB27 AB28 AB29 AB30 AB31 AB32 AB33 AB34 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD I/O VDDP VDDP Pin Number AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AC27 AC28 AC29 AC30 AC31 AC32 AC33 AC34 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 APA1000 Function VDDP VDDP VDDP VDDP VDDP VDDP I/O VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND I/O I/O I/O I/O I/O I/O I/O I/O VDDP I/O VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD I/O VDDP Pin Number AD27 AD28 AD29 AD30 AD31 AD32 AD33 AD34 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AE27 AE28 AE29 AE30 AE31 AE32 AE33 AE34 AF1 AF2 AF3 APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O VDD NC I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O NC VDD VDD I/O GND Pin Number AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF27 AF28 AF29 AF30 AF31 AF32 AF33 AF34 AG1 AG2 AG3 AG4 AG5 AG6 AG7 AG8 AG9 AG10 AG11 AG12 AG13 AG14 APA1000 Function I/O I/O I/O VDDP I/O VDD I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP TCK VDD TRST VDDP I/O I/O I/O GND I/O VDD VDD NC I/O VDD I/O I/O I/O GND I/O I/O I/O I/O I/O I/O 128 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s 1152 FB GA P in 1152 FB GA P in 1152 FB GA P in 115 2 FB GA P in Pin Number AG15 AG16 AG17 AG18 AG19 AG20 AG21 AG22 AG23 AG24 AG25 AG26 AG27 AG28 AG29 AG30 AG31 AG32 AG33 AG34 AH1 AH2 AH3 AH4 AH5 AH6 AH7 AH8 AH9 AH10 AH11 AH12 AH13 AH14 AH15 AH16 AH17 AH18 AH19 AH20 AH21 AH22 AH23 AH24 AH25 APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O VDD I/O NC VDD VDD I/O GND I/O VDDP I/O VDD I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Number AH26 AH27 AH28 AH29 AH30 AH31 AH32 AH33 AH34 AJ1 AJ2 AJ3 AJ4 AJ5 AJ6 AJ7 AJ8 AJ9 AJ10 AJ11 AJ12 AJ13 AJ14 AJ15 AJ16 AJ17 AJ18 AJ19 AJ20 AJ21 AJ22 AJ23 AJ24 AJ25 AJ26 AJ27 AJ28 AJ29 AJ30 AJ31 AJ32 AJ33 AJ34 AK1 AK2 APA1000 Function VDDP I/O VDD TDO VDDP VPN GND I/O VDD I/O NC I/O VDD I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND RCK VDD I/O NC NC GND GND Pin Number AK3 AK4 AK5 AK6 AK7 AK8 AK9 AK10 AK11 AK12 AK13 AK14 AK15 AK16 AK17 AK18 AK19 AK20 AK21 AK22 AK23 AK24 AK25 AK26 AK27 AK28 AK29 AK30 AK31 AK32 AK33 AK34 AL1 AL2 AL3 AL4 AL5 AL6 AL7 AL8 AL9 AL10 AL11 AL12 AL13 APA1000 Function GND I/O VDD I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP TDI VDD VPP GND GND GND GND GND GND GND I/O VDD I/O VDD I/O I/O I/O I/O I/O Pin Number AL14 AL15 AL16 AL17 AL18 AL19 AL20 AL21 AL22 AL23 AL24 AL25 AL26 AL27 AL28 AL29 AL30 AL31 AL32 AL33 AL34 AM1 AM2 AM3 AM4 AM5 AM6 AM7 AM8 AM9 AM10 AM11 AM12 AM13 AM14 AM15 AM16 AM17 AM18 AM19 AM20 AM21 AM22 AM23 AM24 APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD I/O VDD TMS GND GND GND GND GND GND NC GND GND I/O GND I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O v3.0 129 Pr o A S I C P L U S F la s h F a m il y F P GA s 1152 FB GA P in 1 152 FBG A P i n Pin Number AM25 AM26 AM27 AM28 AM29 AM30 AM31 AM32 AM33 AM34 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 AN28 AN29 AN30 AN31 AN32 AN33 AN34 AP2 APA1000 Function I/O GND I/O GND I/O GND GND NC GND GND NC NC GND GND GND NC I/O NC I/O NC I/O GND I/O VDDP VDDP I/O GND GND I/O VDDP VDDP I/O GND I/O NC I/O NC I/O NC GND GND GND NC NC NC Pin Number AP3 AP4 AP5 AP6 AP7 AP8 AP9 AP10 AP11 AP12 AP13 AP14 AP15 AP16 AP17 AP18 AP19 AP20 AP21 AP22 AP23 AP24 AP25 AP26 AP27 AP28 AP29 AP30 AP31 AP32 AP33 APA1000 Function GND GND GND I/O VDD VDD VDD VDD I/O GND I/O VDDP VDDP I/O GND GND I/O VDDP VDDP I/O GND I/O VDD VDD VDD VDD I/O GND GND GND NC 130 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s Li s t o f C ha ng e s The following table lists critical changes that were made in the current version of the document. Previous version Changes in current version (Advanced v3.0) The "ProASICPLUS Product Profile" table on page 1 was updated. The "Ordering Information" section on page 3 was updated. The "Plastic Device Resources" table on page 3 was updated. The "Product Availability" table on page 4 was updated. Table 2 on page 10 was updated. Figure 8 on page 10 is new. Figure 11 on page 12 is new. The Introduction in the "ProASICPLUS Clock Management System" section on page 15 was updated. The "Physical Implementation" section on page 15 was updated. The "Functional Description" section on page 15 was updated. Figure 14 on page 16 through Figure 20 on page 20 were updated. The "PLL Electrical Specifications" table on page 21 was updated. Figure 25 on page 25 was updated. The "Calculating Typical Power Dissipation" section on page 28 was updated. The "Supply Voltages" table on page 30 was updated. The "DC Electrical Specifications (VDDP = 3.3V 0.3V and VDD 2.5V 0.2V)1" table on page 32 was updated. The "Tristate Buffer Delays" table on page 35 was updated. The "Output Buffer Delays" section on page 36 was updated. The"Input Buffer Delays" section on page 37 was updated. "Global Routing Skew" table on page 38 was updated. The"Sample Macrocell Library Listing*" table on page 39 was updated. The "Pin Description" section on page 60 was updated. The following pins have been changed in the "100-Pin TQFP" table on page 63: Pin Number Function Pin Number Function 10 I/O (GLMX1) 60 GL3 11 GL1 61 PPECL2 (I/P) 13 NPECL1 63 NPECL2 15 PPECL1 (I/P) 65 GL4 16 GL2 66 I/O (GLMX2) "144-Pin TQFP" table on page 65 is new. The following pins have been changed in the "208-Pin PQFP" table on page 68: Pin Number Function Pin Number Function 23 I/O (GLMX1) 128 GL3 24 GL1 129 PPECL2 (I/P) 26 NPECL1 132 NPECL2 28 PPECL1 (I/P) 134 GL4 30 GL2 135 I/O (GLMX2) The following pins have been changed in the "456-Pin PBGA" table on page 74: Pin Number Function Pin Number Function M1 GL1 N22 NPECL2 M2 GL2 N23 GL3 M22 GL4 N25 I/O (GLMX2) N2 I/O (GLMX1) P5 NPECL1 N4 PPECL1 (I/P) P26 PPECL2 (I/P) Page page 1 page 3 page 3 page 4 page 10 page 10 page 12 page 15 page 15 page 15 page 16 to page 20 page 21 page 25 page 28 page 30 page 32 page 35 page 36 page 37 page 38 page 39 page 60 v2.0 page 63 page 65 page 68 page 74 v3.0 131 Pr o A S I C P L U S F la s h F a m il y F P GA s Previous version Changes in current version (Advanced v3.0) The following pins have been changed in the "144-FBGA Pin" table on page 86: Pin Number Function Pin Number Function C2 GL2 F9 GL4 D12 I/O (GLMX2 )F11 PPECL2 (I/P E11 NPECL2 F12 GL3 F1 GL1 G1 PPECL1 (I/P) F3 I/O (GLMX1) G4 NPECL1 The following pins have been changed in the "256-Pin FBGA" table on page 89: Pin Number Function Pin Number Function H1 GL1 H16 GL4 H2 NPECL1 J1 GL2 H3 I/O (GLMX1) J2 PPECL1 (I/P) H13 I/O (GLMX2) J13 PPECL2 (I/P) H14 NPECL2 J16 GL3 The following pins have been changed in the"484-Pin FBGA" table on page 96: Pin Number Function Pin Number Function L4 GL1 L19 GL4 L5 NPECL1 M4 GL2 L6 I/O (GLMX1) M5 PPECL1 (I/P) L16 I/O (GLMX2) M16 PPECL2 (I/P) L17 NPECL2 M19 GL3 The following pins have been changed in the "676-FBGA Pin" table on page 103: Pin Number Function Pin Number Function N1 GL1 N25 GL4 N3 I/O (GLMX1) P1 GL2 N5 NPECL1 P5 PPECL1 (I/P) N22 GL3 P22 I/O (GLMX2) N24 NPECL2 P24 PPECL2 (I/P) The following pins have been changed in the "896 FBGA Pin" table on page 112: Pin Number Function Pin Number Function R2 I/O (GLMX1) T3 GL2 R4 NPECL1 T4 PPECL1 (I/P) R5 GL1 T26 PPECL2 (I/P) R27 NPECL2 T27 GL4 R29 I/O (GLMX2) T28 GL3 The following pins have been changed in the "1152 FBGA Pin" table on page 124: Pin Number Function Pin Number Function U4 I/O (GLMX1) U29 NPECL2 U6 NPECL1 U31 I/O (GLMX2) U7 GL1 V28 PPECL2 (I/P) V5 GL2 V29 GL4 V6 PPECL1 (I/P) V30 GL3 Page page 86 page 89 page 96 v2.0 (continued) page 103 page 112 page 124 132 v3.0 Pr o A SI C P L U S F la s h F a m il y F P GA s Previous version Changes in current version (Advanced v3.0) The "Product Availability" table on page 4 was updated. The "Array Coordinates" section on page 10 and Table 2 are new. The "Power-up Sequencing" section on page 12 is new. Table 4 on page 11 was updated. The "Timing Control and Characteristics" section on page 15 was updated. Physical Implementation, Functional Description, Lock Signal, and PLL Configuration Options are new. Figure 14 on page 17 was updated. Figure 15 on page 18 was updated. Sample Implementations, Adjustable Clock Delay, and the "Clock Skew Minimization" section on page 16 are new. Figure 16, Figure 17, Figure 18, Figure 19, and Figure 20 are new. The "PLL Electrical Specifications" table on page 22 is new. The "Design Environment" section on page 27 was updated. Figure 26 on page 27 was updated. The "Calculating Typical Power Dissipation" section on page 29 was updated. The "DC Electrical Specifications (VDDP = 2.5V 0.2V)1" table on page 32 was updated. The "DC Electrical Specifications (VDDP = 3.3V 0.3V and VDD 2.5V 0.2V)1" table on page 33 was updated. The "DC Specifications (3.3V PCI Operation)1" table on page 34 was updated. The "Tristate Buffer Delays" section on page 36 (the figure and table) have been updated. The "Output Buffer Delays" section on page 37 (the figure and table) have been updated. The "Input Buffer Delays" table on page 38 was updated. The "Global Input Buffer Delays" table on page 38 was updated. The "Predicted Global Routing Delay*" table on page 39 was updated. The "Global Routing Skew" table on page 39 was updated. The "Sample Macrocell Library Listing*" table on page 40 was updated. The "Pin Description" section on page 61 was updated. GLMX is new. The "Recommended Design Practice for VPN/VPP" section on page 62 was updated. Pin AK31 of FG1152 for the APA1000 changed to VPP. The "Features and Benefits" section on page 1 were updated. The "ProASICPLUS Product Profile" table on page 1 was updated. The "Ordering Information" section on page 3 was updated. The "Plastic Device Resources" table on page 3 was updated. The "Product Plan" table on page 4 was updated. Table 1 on page 10 was updated. Figure 12 on page 15 was updated. The "Design Environment" section on page 23 was updated. The "Package Thermal Characteristics" table on page 24 was updated. The "Calculating Power Dissipation" section on page 25 was updated. The "Absolute Maximum Ratings*" table on page 26 was updated. The "Programming and Storage and Operating Temperature Limits" table on page 26 was updated. The "Supply Voltages" table on page 26 was updated. The "Recommended Operating Conditions" table on page 26 was updated. The "DC Electrical Specifications (VDDP = 2.5V 0.2V)1" table on page 27 was updated. The "DC Electrical Specifications (VDDP = 3.3V 0.3V and VDD 2.5V 0.2V)1" table on page 28 was updated. The "Synchronous Write and Read to the Same Location" figure on page 44 was updated. The "Asynchronous Write and Synchronous Read to the Same Location" figure on page 45 was updated. The "Asynchronous FIFO Read" figure on page 50 was updated. The "Pin Description" section on page 57 has been updated. The "Recommended Design Practice for VPN/VPP" section on page 57 is new. The "100-Pin TQFP" figure on page 62 is new. The "484-Pin FBGA" figure on page 96 is new. The description for the VPN pin has changed. Page page 4 page 10 page 12 page 11 page 15 to page 16 page 17 page 18 page 16 page 19 to page 21 page 22 page 27 page 27 page 29 page 32 page 33 page 34 page 36 page 37 page 38 page 38 page 39 page 39 page 40 page 61 page 62 page 128 page 1 page 1 page 3 page 3 page 4 page 10 page 15 page 23 page 24 page 25 page 26 page 26 page 26 page 26 page 27 page 28 page 44 page 45 page 50 page 57 page 57 page 62 page 96 page 57 Advanced v0.7 (Advanced v0.6) Advanced v0.5 v3.0 133 P r o A S IC P L U S F l a sh F a m ily F P GA Previous version Changes in current version (Advanced v3.0) Page Advanced v0.4 The "Plastic Device Resources" table on page 3 has been updated. Figure 12 and Figure 13 on page 15 have been updated. The "Tristate Buffer Delays" table on page 31 has been updated. The "Output Buffer Delays" table on page 32 has been updated. The "Input Buffer Delays" table on page 33 has been updated. The "Global Input Buffer Delays" table on page 34 has been updated. The "456-Pin PBGA" table on page 74 has been updated. The "676-FBGA Pin" table on page 103 has been updated. The "ProASICPLUS Product Profile" figure on page 1 has been changed. The "Plastic Device Resources" figure on page 3 has been updated. The Supply Voltages table on page 10 has been updated. WDATA has ben changed to DI, and RDATA has been changed to DO to make them consistent with the signal names found in the Macro Library Guide. Figure 13 on page 19 and Figure 14 on page 20 have been updated. page 3 page 15 page 31 page 32 page 33 page 34 page 74 page 103 page 1 page 3 page 10 Advanced v0.3 Advanced v0.1 page 19 and page 20 The "Design Environment" figure on page 23 and Figure 18 on page 23 have been page 23 updated. and page 23 The table in the "Package Thermal Characteristics" section on page 24 has been updated. page 24 The "Calculating Power Dissipation" section on page 25 is new. page 25 The "Programming and Storage and Operating Temperature Limits" section on page 26 is page 26 new. The "Supply Voltages" section on page 26 has been updated. page 26 The "DC Electrical Specifications (VDDP = 2.5V 0.2V)1" table on page 27 was updated. page 27 The "DC Electrical Specifications (VDDP = 3.3V 0.3V and VDD 2.5V 0.2V)1" table on page 28 page 28 was updated. The "AC Specifications (3.3V PCI Revision 2.2 Operation)" table on page 30 was updated. page 30 The "Clock Conditioning Circuit" section on page 14 was updated. page 14 Figure 12 on page 15 was updated. page 15 Figure 13 on page 15 is new. page 15 Tables 5, 6, and 7 from Advanced v0.3 were removed. The "Memory Block SRAM Interface Signals" figure on page 19 was updated. page 19 The "Memory Block FIFO Interface Signals" figure on page 48 was updated. page 48 All pinout tables have been updated, and several packages are new: 208-Pin PQFP - APA150, APA300, APA450, APA600 456-Pin PBGA - APA150, APA300, APA450, APA600 144-Pin FBGA - APA150, APA300, APA450 256-Pin FBGA - APA150, APA300, APA450, APA600 676-Pin FBGA - APA600 Figure 15 on page 21 has been updated page 21 D at a s h e et C a t e g o r i e s In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advanced," "Production." The definition of these categories are as follows: P rod uct B ri ef The product brief is a modified version of an advanced datasheet containing general product information. This brief summarizes specific device and family information for unreleased products. Adv anc ed This datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. Unm ar ked (pr odu ct ion) This datasheet version contains information that is considered to be final. 134 v3.0 Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. http://www.actel.com Actel Corporation 955 East Arques Avenue Sunnyvale, California 94086 USA Tel: (408) 739-1010 Fax: (408) 739-1540 Actel Europe Ltd. Dunlop House, Riverside Way Camberley, Surrey GU15 3YL United Kingdom Tel: +44 (0)1276 401450 Fax: +44 (0)1276 401490 Actel Japan EXOS Ebisu Bldg. 4F 1-24-14 Ebisu Shibuya-ku Tokyo 150 Japan Tel: +81 03-3445-7671 Fax: +81 03-3445-7668 Actel Hong Kong 39th Floor One Pacific Place 88 Queensway Admiralty, Hong Kong Tel: 852-22735712 5172161-8/5.03 |
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